/*
** estimate.h -- constants for area/speed estimation - generated from
** data for Bell Labs shuttle run (2.5 micron, single level metal process)
** Joseph B. Evans, 9/19/88
*/

#define DEF_PR 2.5	/* default process line width in microns */
#define MINBITS 2	/* minimum number of bits for estimation */
#define MAXBITS 20	/* maximum number of bits for estimation */
#define INITAPS 1	/* initial number of taps */

/* size estimates for components - length in microns */
#define X_NAND 34.5		/* nand gate */
#define Y_NAND 50.25
#define X_GATE 34.5		/* generic gate */
#define Y_GATE 50.25
#define X_FA 148.0		/* full adder */
#define Y_FA 118.25
#define X_MULTP X_FA		/* parallel multiplier cell = full adder */
#define Y_MULTP Y_FA
#define X_BKADD 220.25		/* brent-kung adder */
#define Y_BKADD 62.5
#define X_DFF 69.0		/* one bit d flip-flop */
#define Y_DFF 65.0
#define X_PTQS 91.25		/* parallel power-of-two quantizer shift */
#define Y_PTQS 77.0
#define X_PTQQ 216.5		/* parallel power-of-two ripple quantizer */
#define Y_PTQQ 77.0
#define X_LATCH 166.0		/* one bit latch cell */
#define Y_LATCH 56.25
#define X_SRAM 47.5		/* one bit static ram cell */
#define Y_SRAM 69.5
#define X_RAMROW 43.75		/* ram row decoder cell */
#define Y_RAMROW 55.0
#define X_VSSHFT X_PTQS		/* variable step size shift cell */
#define Y_VSSHFT Y_PTQS
#define X_VSUPS 48.0		/* variable step size update ss shift */
#define Y_VSUPS 273.5
#define X_VSUPL 49.0		/* variable step size update logic */
#define Y_VSUPL 273.5
#define X_MULTSP 166.5		/* serial-parallel multiplier bit slice */
#define Y_MULTSP 299.0
#define X_PTQL 132.3		/* serial power-of-two quantizer logic */
#define Y_PTQL 132.3
#define X_VSSL 116.2		/* serial vs shift logic */
#define Y_VSSL 116.2

/* speed estimates for components - time in ns */
#define T_NAND 5		/* nand gate */
#define T_GATE T_NAND		/* generic gate */
#define T_DFF 20		/* one bit d flip-flop */
#define T_LATCH T_DFF		/* one bit latch cell */
#define T_FA 9			/* full adder */
#define T_MULTP T_FA		/* parallel multiplier cell = full adder */
#define T_MULTSP 9		/* serial-parallel multiplier slice */
#define T_PTQS 4		/* parallel power-of-two quantizer shift */
#define T_PTQQ 7		/* parallel power-of-two ripple quantizer */
#define T_BKADD 8		/* brent-kung adder slice */
#define T_VSSHFT T_PTQS		/* variable step size shift */
#define T_VSUPS 5		/* variable step size update ss shift */
#define T_VSUPL 5		/* variable step size update logic */
#define T_SRAMW 9		/* one bit static ram write */
#define T_SRAMR 8		/* one bit static ram read */
#define T_RAMROW 12		/* ram row decoder cell */
#define T_PTQL 8		/* power-of-two serial shift logic */
#define T_VSSL 8		/* variable step size serial shift logic */

/* define area estimation structure */ 
struct space {
	double dff_x;
	double dff_y;
	double fa_x;
	double fa_y;
	double multsp_x;
	double multsp_y;
	double multp_x;
	double multp_y;
	double vsupl_x;
	double vsupl_y;
	double vsups_x;
	double vsups_y;
	double vsshft_x;
	double vsshft_y;
	double ptqs_x;
	double ptqs_y;
	double ptqq_x;
	double ptqq_y;
	double ptql_x;
	double ptql_y;
	double bkadd_x;
	double bkadd_y;
	double sram_x;
	double sram_y;
	double ramrow_x;
	double ramrow_y;
	double latch_x;
	double latch_y;
	double vssl_x;
	double vssl_y;
} a;

/* define speed (time) estimation structure */ 
struct speed {
	double dff;
	double fa;
	double multsp;
	double multp;
	double vsupl;
	double vsups;
	double vsshft;
	double ptqs;
	double ptqq;
	double ptql;
	double bkadd;
	double sramw;
	double sramr;
	double ramrow;
	double latch;
	double vssl;
} t;

/* define quantization size structure */ 
struct quant {
	int data;
	int coef;
	int err;
} q;

/* define quantization size structure */ 
struct vs {
	int m0;
	int m1;
	int ss;
} v;

/* define processing element structure */ 
struct pe {
	double x;
	double y;
	double area;
	double time;
};

int dedicate;
int multi;
int parallel;
int serial;
int taps;

#define max(x,y) ((x>y)?(x):(y))