From athanas@pequod.ee.vt.edu Fri Aug  4 06:20:37 1995
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Date: Fri, 4 Aug 95 09:18:38 EDT
From: athanas@pequod.ee.vt.edu (Peter Athanas)
Message-Id: <9508041318.AA07617@pequod.ee.vt.edu.ee.vt.edu>
To: gigaops@gigaops.com
Subject: hif.vhd
Status: O

--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||
--||
--||  VHDL model for the HPGA interface module originally written by
--||  B. Taylor (GigaOps), and adapted by P. Athanas (Virginia Tech), 
--||  6/95.
--||
--||  NOTE:  This has been checked-out, and seems to work fine;
--||  however, if you should notice odd behavior that necessitates
--||  repair, please report it to athanas@vt.edu.
--||
--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY hif_444 IS
PORT (
   hbus_datain		: in Std_Logic_Vector(15 downto 0);
   hbus_selectin	: in Std_Logic;
   hbus_selectout	: out Std_Logic;
   hbus_selecten	: out Boolean;
   hbus_func		: in Std_Logic_Vector(3 downto 0);
   hbus_ok		: out Std_Logic;
   host_reg_addr	: out Std_Logic_Vector(7 downto 0);   
   host_mod_addr	: inout Std_Logic_Vector(3 downto 0);   
   host_rd_reg		: inout Boolean;
   host_call_fun	: inout Boolean;	
   host_rd_reg0		: out Boolean;
   host_rd_reg1		: out Boolean;
   host_rd_reg2		: out Boolean;
   host_rd_reg3		: out Boolean;
   host_wr_reg		: inout Boolean;
   host_wr_reg0		: out Boolean;
   host_wr_reg1		: out Boolean;
   host_wr_reg2		: out Boolean;
   host_wr_reg3		: out Boolean;
   host_call_fun0	: out Boolean;
   host_call_fun1	: out Boolean;
   host_call_fun2	: out Boolean;
   host_call_fun3	: out Boolean;
   host_fun_return	: in Std_Logic;
   host_mod_status	: in Std_Logic;
   C			: in Std_Logic );
END hif_444;

ARCHITECTURE fpga OF hif_444 IS
   SIGNAL amod, areg		: Std_Logic_Vector(3 downto 0);
   SIGNAL host_wr_id		: Boolean;
   SIGNAL host_rd_status	: Boolean;

   SIGNAL Clock			: Std_Logic;
   SIGNAL areg0, areg1		: Boolean;
   SIGNAL areg2, areg3		: Boolean;

   SIGNAL mod_selected		: Boolean;
   SIGNAL mod_select		: Boolean;
   SIGNAL host_wr_id_d		: Boolean;
   SIGNAL mrd_or_mwr		: Boolean;
BEGIN
   Clock <= C;
   hbus_selectout <= host_mod_status;

   amod <= hbus_datain(11 downto 8);
   areg <= hbus_datain(7 downto 4);

   areg0 <= areg = "0000";
   areg1 <= areg = "0001";
   areg2 <= areg = "0010";
   areg3 <= areg = "0011";

   host_rd_status <= hbus_func = "0001";
   host_rd_reg <= hbus_func = "0010";
   host_wr_reg <= hbus_func = "0011";
 
   mod_select  <= amod = host_mod_addr;
   -- these signals become active in the 3rd cycle (cycle 2)
   host_call_fun0 <= (host_call_fun AND areg0) AND mod_selected;
   host_call_fun1 <= (host_call_fun AND areg1) AND mod_selected;
   host_call_fun2 <= (host_call_fun AND areg2) AND mod_selected;
   host_call_fun3 <= (host_call_fun AND areg3) AND mod_selected;

   PROCESS BEGIN
      WAIT UNTIL Clock'event AND Clock = '1';
      -- the following decode is sequential:
      host_call_fun <= hbus_func = "0101";
      host_wr_id <= hbus_func = "0111";

      -- implement hbus functions:
      host_wr_id_d <= host_wr_id;
      IF host_wr_id_d THEN
         IF hbus_selectin = '1' THEN
            host_mod_addr <= hbus_datain(3 downto 0);
         END IF;
         mod_selected <= hbus_selectin = '1';
      END IF;
      
      hbus_selecten <= host_rd_status;


      IF (hbus_func = "0010") OR ((hbus_func = "0011") OR (hbus_func = "0101")) THEN
         IF mod_select THEN
            host_reg_addr <= hbus_datain(7 downto 0);
         END IF;
         mod_selected <= mod_select; 
      END IF;

      -- if selected:
      IF mod_selected THEN 
         mod_selected <= FALSE;
      END IF;

      mrd_or_mwr <= host_rd_reg OR host_wr_reg;

      IF (mod_selected AND mrd_or_mwr) OR host_fun_return = '1' THEN 
         hbus_ok <= '1';
      ELSE
         hbus_ok <= '0';
      END IF;

      host_rd_reg0 <= host_rd_reg AND (areg0 AND mod_select);
      host_rd_reg1 <= host_rd_reg AND (areg1 AND mod_select);
      host_rd_reg2 <= host_rd_reg AND (areg2 AND mod_select);
      host_rd_reg3 <= host_rd_reg AND (areg3 AND mod_select);

      host_wr_reg0 <= host_wr_reg AND (areg0 AND mod_select);
      host_wr_reg1 <= host_wr_reg AND (areg1 AND mod_select);
      host_wr_reg2 <= host_wr_reg AND (areg2 AND mod_select);
      host_wr_reg3 <= host_wr_reg AND (areg3 AND mod_select);

   END PROCESS;
END;