From athanas@pequod.ee.vt.edu Fri Aug  4 06:22:24 1995
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Date: Fri, 4 Aug 95 09:20:26 EDT
From: athanas@pequod.ee.vt.edu (Peter Athanas)
Message-Id: <9508041320.AA07621@pequod.ee.vt.edu.ee.vt.edu>
To: gigaops@gigaops.com
Subject: xfpga.vhd
Status: O

--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||
--||  Synthesizable model for XFPGA 
--||  5/95 P.Athanas (Virginia Tech)
--||
--||  This model configures the XFPGA to respond to simple
--||  commands from the YFPGA.  I use this to initialize the SRAM
--||  on the XFPGA.  This is used in a driver which first uses this
--||  configuration to download a program into the XFPGA memory, then
--||  reconfigures to a processor design for subsequent execution of
--||  the downloaded program.  
--||
--||  IMPORTANT NOTE: since WR_L and ADDRESS are cleared during 
--||  reconfiguration, memory location 0 IS NOT USABLE!!
--||
--||  NOTE:  This has been checked-out, and seems to work fine;
--||  however, if you should notice odd behavior that necessitates
--||  repair, please report it to athanas@vt.edu.
--||
--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||--||
 
  

LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY xfpga IS
PORT (
   xbus_clk	: in Std_Logic;
   xbus_clk2x	: in Std_Logic;
   wbus_clk	: in Std_Logic;
   wbus_clk2x	: in Std_Logic;
   xbus0	: inout Std_Logic_Vector(15 downto 0);
   xbus1	: inout Std_Logic_Vector(15 downto 0);
   xbus2	: inout Std_Logic_Vector(15 downto 0);
   xbus3	: inout Std_Logic_Vector(15 downto 0);
   xfunc_b	: in Std_Logic;
   qmem_addr	: in Std_Logic_Vector(11 downto 2);
   qmem_ras_b	: out Std_Logic;
   pmem_ras_b	: out Std_Logic;
   qmem_cas_b	: out Std_Logic;
   qmem_rd_b	: out Std_Logic;
   qmem_wr_b	: out Std_Logic;
   xmem_data	: inout Std_Logic_Vector(15 downto 0);
   xmem_addr	: out Std_Logic_Vector(15 downto 0);
   xmem_ras_b	: out Std_Logic;
   xmem_cas_b	: out Std_Logic;
   xmem_rd_b	: out Std_Logic;
   xmem_wr_b	: out Std_Logic;
   xmem_se_b	: out Std_Logic;
   xmem_ext_b	: out Std_Logic;
   pic_clk	: in Std_Logic;
   pq_pclk	: in Std_Logic;
   pq_sclk	: in Std_Logic;
   xpga_init	: in Std_Logic;
   hbus_sel	: in Std_Logic;
   xpga_tms	: in Std_Logic;
   dbug_dout	: in Std_Logic;
   qmem_data	: inout Std_Logic_Vector(15 downto 0);
   pq_func	: inout Std_Logic_Vector(10 downto 0) );
END xfpga;

ARCHITECTURE fpga OF xfpga IS

   SIGNAL clock		: Std_Logic;
   SIGNAL ready		: Std_Logic;
   SIGNAL xfunc		: Std_Logic_Vector(1 downto 0);
   SIGNAL qdata_in	: Std_Logic_Vector(15 downto 0);
   SIGNAL qdata_out	: Std_Logic_Vector(15 downto 0);
   SIGNAL xdata_in	: Std_Logic_Vector(15 downto 0);
   SIGNAL xdata_out	: Std_Logic_Vector(15 downto 0);
   SIGNAL y_addr	: Std_Logic_Vector(15 downto 0);

   TYPE StateVec IS (IDLE, NOP, READ1, WRITE1, READ2,
                     WRITE2, READ3, WRITE3, READ4, WRITE4);
   SIGNAL State         : StateVec;
 
   CONSTANT XREAD	: Std_Logic_Vector(1 downto 0) := "01";
   CONSTANT XWRITE	: Std_Logic_Vector(1 downto 0) := "10";
BEGIN
   
   -- initialized unused pins
   pmem_ras_b <= '1';
   qmem_ras_b <= '1';
   xmem_ras_b <= '1';
   qmem_cas_b <= '1';
   xmem_cas_b <= '1';

   clock <= pq_sclk;
   pq_func(9 downto 0) <= "ZZZZZZZZZZ";
   xfunc <= pq_func(8 downto 7);
   pq_func(10) <= ready;
   y_addr <= qmem_addr & pq_func(5 downto 0);

   -- Corresponding state machine that performs reads and
   -- writes to local memory.  See (sparse) comments in yfpga.vhd
   -- for details.
   PROCESS 
   BEGIN
      WAIT UNTIL clock'event AND clock= '1';
      CASE State IS
      WHEN IDLE =>
	 xmem_rd_b <= '1';
	 xmem_wr_b <= '1';
	 ready <= '0';
         IF xfunc = XREAD THEN 
            State <= READ1;
	    xmem_se_b <= '0';
         ELSIF xfunc = XWRITE THEN 
            State <= WRITE1;
	    xmem_se_b <= '0';
	 ELSE
	    State <= IDLE;
	    xmem_se_b <= '1';
	 END IF;

      WHEN READ1 =>
	 xmem_addr <= y_addr;
	 xmem_rd_b <= '0';
	 State <= READ2;

      WHEN READ2 =>
	 qdata_out <= xdata_in;
	 xmem_rd_b <= '0';
	 ready <= '1';
	 State <= READ3;
      WHEN READ3 =>
	 xmem_rd_b <= '1';
	 ready <= '0';
	 State <= IDLE;


      WHEN WRITE1 =>
	 xmem_addr <= y_addr;
	 xmem_wr_b <= '1';
	 ready <= '0';
	 xdata_out <= qdata_in;
	 State <= WRITE2;
      WHEN WRITE2 =>
	 xmem_wr_b <= '0';
	 State <= WRITE3;
	 ready <= '0';
      WHEN WRITE3 =>
	 ready <= '1';
	 xmem_wr_b <= '1';
	 State <= WRITE4;
      WHEN WRITE4 =>
	 xmem_wr_b <= '1';
	 ready <= '0';
	 State <= IDLE;

      WHEN OTHERS =>
	 State <= IDLE;
      END CASE;
   END PROCESS;

   xmem_data <= xdata_out WHEN ((State = WRITE2) OR State = WRITE3) OR (State = WRITE4) ELSE
		"ZZZZZZZZZZZZZZZZ";
   qmem_data <= qdata_out WHEN (State = READ2) OR (State = READ3) ELSE
		"ZZZZZZZZZZZZZZZZ";
   qdata_in <=  qmem_data ;
   xdata_in <=  xmem_data ;
END;