------------------------------------------------------------------- Voltage thresholds: VTN 0.4 - 0.9 VTP 0.4 - 0.9 Transconductance: Nbeta micro-mhos/volt 53-78 Pbeta micro-mhos/volt 16-25 Sheet Resistivities: TaSi sheet res. 2-4 ohms N+ sheet res. 24-36 P+ sheet res. 92-138 Gate ox thickness 300-400 Angstroms ------------------------------------------------------------------- /* file "mulga/include/cmostech2.5.h" */ /* master technology file BTL 2.5u twin-tub */ #define PROCESS "2.5" #define SNAP_DIST 250 #define TUB_PROCESS 'P' /* Ptub process */ #define NA 0 /* not available */ /* fat wires */ #define FAT_WIRE_SIZE NA #define FAT_WIRE_SPACING_INCREASE NA #define WIDE_M1_WIDTH 6000 #define WIDE_M1_SPACING_INCREASE 250 #define WIDE_M2_WIDTH NA #define WIDE_M2_SPACING_INCREASE NA /* device dimensions */ #define DEVICE_POLY_WIDTH 5000 #define DEVICE_POLY_LENGTH 3000 #define DEVICE_NPOLY_LENGTH 3000 #define DEVICE_PPOLY_LENGTH 3000 #define DEVICE_DIFF_WIDTH 5000 #define DEVICE_DIFF_LENGTH 2500 #define DEVICE_POLY_OVERLAP 2000 #define DEVICE_NPLUS_OVERLAP 2000 #define PTUB_OVERLAP 5000 #define NTUB_OVERLAP 5000 #define LOAD_DIFF_LENGTH 2500 #define LOAD_DIFF_WIDTH 2500 #define LOAD_POLY_LENGTH 2500 #define LOAD_POLY_WIDTH 10000 /* wire widths */ #define ALUM_WIRE_WIDTH 2500 #define POLY_WIRE_WIDTH 2500 #define DIFF_WIRE_WIDTH 2500 #define MP_POLY_WIDTH 4500 #define MP_ALUM_WIDTH 5000 #define MD_DIFF_WIDTH 5000 #define MD_ALUM_WIDTH 5000 #define MD_THINOX_WIDTH 4500 #define PD_POLY_WIDTH 5000 #define PD_ALUM_WIDTH 5000 #define PD_DIFF_WIDTH 5000 #define PD_POLY_LENGTH 1500 #define PD_ALUM_LENGTH 3000 #define PD_DIFF_LENGTH 1500 #define M12_ALUM_WIDTH NA #define M12_ALUM2_WIDTH NA #define NPLUS_CONTACT_WIDTH 8500 #define PTUB_CONTACT_WIDTH 7250 /* actually half width */ #define NTUB_CONTACT_WIDTH 7250 /* actually half width */ #define PTUB_TRANCONT_WIDTH 7250 /* actually half width */ #define NTUB_TRANCONT_WIDTH 7250 /* actually half width */ #define CONTACT_CUT_WIDTH 2500 #define CONTACT2_CUT_WIDTH NA #define ALUM2_WIRE_WIDTH NA /* not in 2.5u process */ /* overlaps */ #define PPLUS_OVERLAP 500 #define POLY_DIFF_OVERLAP 2500 #define DIFF_POLY_OVERLAP 2500 #define OVERLAP 1000 #define NPLUS_OVERLAP_NTUB 2000 /* nplus extension beyond ntub contact R11 */ #define PPLUS_OVERLAP_PTUB NA #define NPLUS_OVERLAP_NTOX 2000 /* nplus extension beyond nthinox R11 */ #define PPLUS_OVERLAP_PTOX NA /* spacings */ #define ALUM2_ALUM2_SPACE NA /* not in 2.5 process */ #define ALUM2_ALUM_SPACE NA /* not in 2.5 process */ #define ALUM2_POLY_SPACE NA /* not in 2.5 process */ #define ALUM2_DIFF_SPACE NA /* not in 2.5 process */ #define ALUM_ALUM_SPACE 2500 #define POLY_POLY_SPACE 2500 #define POLY_DIFF_SPACE 1250 #define ALUM_POLY_SPACE 0 #define ALUM_DIFF_SPACE 0 #define NDIFF_PDIFF_SPACE 10000 #define DIFF_DIFF_SPACE 3500 #define NPLUS_VSSP_SPACE 2000 #define NPLUS_NPLUS_SPACE 3000 #define PDIFF_VDDN_SPACE 2000 #define PDIFF_PTUB_SPACE 5000 #define NDIFF_NTUB_SPACE 5000 #define CONTACT_CONTACT_SPACE 2500 #define CONTACT_DIFF_SPACE 2500 #define CONTACT_GATE_SPACE 2000 #define CONTACT2_CONTACT2_SPACE NA /* not in 2.5 process */ #define CONTACT2_CONTACT_SPACE NA /* not in 2.5 process */ #define CONTACT2_DIFF_SPACE NA /* not in 2.5 process */ #define CONTACT2_GATE_SPACE NA /* not in 2.5 process */ #define MAX_SPACE 10000 #define ACTIVE_ACTIVE_SPACE 0 /* perimeter zones */ #define ALUM2_PERIM_ZONE NA /* not in 2.5 process */ #define ALUM_PERIM_ZONE 1250 #define POLY_PERIM_ZONE 1250 #define DIFF_PERIM_ZONE 2000 #define VCON_PERIM_ZONE 2000 #define POLY2_PERIM_ZONE 875 #define POLY2_WIRE_WIDTH 1750 #define PD_POLY2_WIDTH 3750 #define PD_POLY2_LENGTH 3750 #define POLYCON_WIDTH 1750 /* compatibility with 1.75u */ #define POLY2_POLYCON_OVERLAP 750 #define POLY2_DIFF_OVERLAP 500 #define POLY_POLYCON_OVERLAP 1000 #define POLY2_POLY2_SPACE 1750 #define CONTACT_POLY2_SPACE 2000 #define POLYCON_THINOX_SPACE 1500 #define POLYCON_POLY_SPACE 1750 /* capacitances */ #define POLYCAP 28 #define ALUMCAP 22 #define NDIFCAP 246 #define PDIFCAP 228 #define NTCAP 2300 #define PTCAP 2100 #define GATECAP 1727 #define NGATECAP 1727 #define PGATECAP 1727 /* * The values below are used by the advice to emu circuit compiler, * and are in e-18. They have been taken from /image/usr/rac/advice/lib2.5 * Emu is expecting femto farads e-15. */ #define POLTOX 1150 /* Area */ #define CMTOSH 221 /* Unit length of default width */ #define CM2TOSH 0 /* NA - Unit length of default width */ #define CPTOSH 265 /* Unit length of default width */ /* * The values below are for zero volt bias. The fudge value yields a * fixed value capacitor that gives similar delay times, as the * voltage dependant diode capacitor. */ #define DIODE_FUDGE_N 0.6 #define DIODE_FUDGE_P 0.6 #define DIODE_N_AREA 480 #define DIODE_N_PER 752 #define DIODE_P_AREA 488 #define DIODE_P_PER 651 #define GATE_OV 335 /* (0.3 * POLTOX), Fixed Capacitance of the Gate to Source/Drain, as seen by the GATE. */ #define GATE_SD 446 /* (0.4 * POLTOX), Fixed Capacitance of the Gate to Source/Drain, as seen by the Source or Drain. */ /* Anti-feature tolerances (for maskclean) */ #define ANTI_FEATURE_TOLERANCE 1500 #define BOUNDARY_TOLERANCE 1500 /**************************************************************************** * The following anti-features-tolerances, are directly related to (5x) * the compensation values that are used during a ledge run. Be sure to * check with fabrication before running the final maskclean. RAC ****************************************************************************/ #define NTHIN_ANTI_FEAT_TOL 3250 #define NTHIN_ANTI_BOUN_TOL 3250 #define PTHIN_ANTI_FEAT_TOL 3250 #define PTHIN_ANTI_BOUN_TOL 3250 #define POLYS1_ANTI_FEAT_TOL 2250 #define POLYS1_ANTI_BOUN_TOL 2250 #define METAL1_ANTI_FEAT_TOL 2250 #define METAL1_ANTI_BOUN_TOL 2250 #define NPLUS_ANTI_FEAT_TOL 3000 #define NPLUS_ANTI_BOUN_TOL 3000 #define NTUB_ANTI_FEAT_TOL 5000 /* This is == to design rule, because all tubs should be connected */ #define NTUB_ANTI_BOUN_TOL 5000 #define CSTOP_ANTI_FEAT_TOL 0 /* Not used as XYMASK in this process */ #define CSTOP_ANTI_BOUN_TOL 0 #define PTUB_ANTI_FEAT_TOL 5000 #define PTUB_ANTI_BOUN_TOL 5000 #define NGATE_ANTI_FEAT_TOL 1750 /* This was at 2250, but gates can */ #define NGATE_ANTI_BOUN_TOL 1750 /* get closer than this when they */ #define PGATE_ANTI_FEAT_TOL 1750 /* are side by side with no contact */ #define PGATE_ANTI_BOUN_TOL 1750 /* between them. */ /******************************************************************************* * Compensation values ******************************************************************************/ #define NPLUS_COMP 0 #define NTHIN_COMP 750 #define PTHIN_COMP 750 #define POLY_COMP 250 #define METAL_COMP 250 #define PTUB_COMP 1000 #define NTUB_COMP 0 #define CHANSTOP_COMP 1000