BSIM USER'S GUIDE FOR MOSIS February 20, 1986 ************************************************************ This is a supplement to the original "SPICE Version 2G User's Guide," and is intended for SPICE users who have access to BSIM (Berkeley Short-channel Igfet Model). It contains descriptions of the various additional device features supported by BSIM and how to activate them. To be complete, it should be used together with the original User's Guide. ************************************************************ In addition to the regular resistor and capacitor for- mats, BSIM also supports resistors and capacitors generated with interconnects. 1. Resistors General form: RXXXXXXX N1 N2 PNAME_LT L=VAL > Examples: R1 1 2 PC1_DU1 L=10U RC1 12 17 PC1_DU3 L=20U W=4U TC=0.001, 0.015 N1 and N2 are the two element nodes. PNAME is the pro- cess name. LT is the interconnect type. At present, there are fourteen interconnect types available (DU1 to DU6, PY1 to PY4, and ML1 to ML4). L and W are the resistor length and width, in meters. W should be specified if the default value in the process file is not to be used. TC1 and TC2 are the (optional) temperature coeffi- cients; if not specified, zero is assumed for both. The value of the resistor as a function of temperature is given by: value(TEMP) = value(TNOM)*(1+TC1*(TEMP-TNOM)+TC2*(TEMP- TNOM)**2)) 2. Capacitors General form: CXXXXXXX N1 N2 PNAME_LT L=VAL Examples: CBYP 13 0 PC1_PY1 L=20U COSC 17 23 PC1_ML2 L=30U W=30U IC=3V -2- N1 and N2 are the two element nodes. PNAME is the pro- cess name. LT is the interconnect type. At present, there are fourteen interconnect types available (DU1 to DU6, PY1 to PY4, and ML1 to ML4). L and W are the capacitor length and width, in meters. W should be specified if the default value in the process file is not to be used. The (optional) initial condition is the initial (time-zero) value of capacitor voltage (in volts). [Note that the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN card.] 3. BSIM MOSFET's General form: SXXXXXXX ND NG NS NB PNAME_MT_DT<_STHD> + + Examples: S1 24 2 0 20 PC1_NM1 S31 2 17 6 10 PC2_NM2_DU2_STHD L=5U W=2U S31 2 16 6 10 PC2_PM1_DU3 5U 2U S1 2 9 3 0 PC2_PM2_DU3 L=10U W=5U AD=100P AS=100P PD=40U PS=40U S1 2 9 3 0 PC1_NM1_STHD 10U 5U 2P 2P ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively. PNAME is the process name. MT is the device type. At present, there are five device types for both N-channel and P-channel transistors (NM1 to NM5, and PM1 to PM5). DT is the diffusion type to be used for the source/drain junctions. There are six diffusion types available (DU1 to DU6). The default is DU1 for N-channel transistors and DU2 for P-channel transistors. STHD is used as a flag. If it is specified, the weak- inversion current characteristic will be included. L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffu- sions, in sq-meters. [Note that the suffix U specifies microns (1E-6 m) and P sq-microns (1E-12 sq-m). If any of L, W, AD, or AS are not specified, default values are used. The user may specify the values to be used for these default parameters on the .OPTIONS card. The use of defaults simplifies input deck preparation, as well as the editing required if device geometries are to be changed.] PD and PS are the perimeters of the drain and source junctions, in meters. NRD and NRS designate the equivalent -3- number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on the .process card for an accurate representation of the series drain and source resistance components of each transistor. [PD, PS, NRD, and NRS all default to 0.0. OFF indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using IC=VDS,VGS,VBS is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired start- ing from other than the quiescent operating point. See the .IC card for a better and more convenient way to specify transient initial conditions.] 4. .PROCESS Card General form: .PROCESS PNAME FILENAME=FNAME Examples: .PROCESS PC1 FILENAME=PNMED .PROCESS PD2 FILENAME=FAST The .PROCESS card specifies process parameter values that will be used by one or more devices. PNAME is the process name, and FNAME is the name of the file containing the process parameter values. Special rules have to be observed in choosing FNAME. The leading character of FNAME should be alphabetical. Alphabetical characters will be recognized only in the capital form. Totally no more than 8 characters are allowed. The process card is used together with resistors, capacitors, as well as MOS transisors. 5. Process File This file is generated by the automated characteriza- tion program, and it contains the process information for the transistors as well as for the interconnects. For transistors, the L (channel-length) and W (channel-width) sensitivity factors of a basic electrical parameter are denoted by appending the italic characters 'l' and 'w' to the name of the parameter. For the example of the basic parameter VFB (flat-band voltage), there are two correspond- ing sensitivity factors, VFBl, VFBw. If P0 is the basic parameter and PL and PW are the corresponding L and W sensi- tivity factors. The formula PL PW P = P0 + ---- + ---- Leff Weff is used to obtained the value for each transistor size with both Leff (= LMK - /_\_L) and Weff (= WMK - /_\_W) in um. -4- (a) The format of the process parameters is listed below: TRANSISTORS name L sens. factor W sens. factor units of basic parameter 1 VFB (VFB) VFBl (LVFB) VFBw (WVFB) V 2 o|S (PHI) o|Sl (LPHI) o|Sw (WPHI) V 3 K1 (K1) K1l (LK1) K1w (WK1) V**1/2 4 K2 (K2) K2l (LK2) K2w (WK2) - 5 n0 (ETA) n0l (LETA) n0w (WETA) - 6 uZ (MUZ) d`l (DL) d`w (DW) cm**2/ V-s(um,um) 7 U0Z (U0) U0Zl (LU0) U0Zw (WU0) V**-1 8 U1Z (U1) U1Zl (LU1) U1Zw (WU1) umV**-1 9 uZB (X2MZ) uZBl (LX2MZ) uZBw (WX2MZ) cm**2/V**2-s 10 nB (X2E) nBl (LX2E) nBw (WX2E) V**-1 11 nD (X3E) nDl (LX3E) nDw (WX3E) V**-1 12 U0B (X2U0) U0Bl (LX2U0) U0Bw (WX2U0) V**-2 13 U1B (X2U1) U1Bl (LX2U1) U1Bw (WX2U1) umV**-2 14 uS (MUS) uSl (LMS) uSw (WMS) cm**2/V**2-s 15 uSB (X2MS) uSBl (LX2MS) uSBw (WX2MS) cm**2/V**2-s 16 uSD (X3MS) uSDl (LX3MS) uSDw (WX3MS) cm**2/V**2-s 17 U1D (X3U1) U1Dl (LX3U1) U1Dw (WX3U1) umV**-2 18 Tox (TOX) Temp (TEMP) Vdd (VDD) um(0C,V) 19 CGDO CGSO CGBO F/m 20 XPART DUM1 DUM2 - 21 N0 LN0 WN0 - 22 NB LNB WNB - 23 ND LND WND - ---------- ------------------------------------------------------------------------------------ INTERCONNECTS 1 Rsh (RSH) Cj (CJ) Cjw (CJW) Ijs (IJS) Pj (PJ) 2 Pjw (PJW) Mj (MJ) Mjw (MJW) Wdf (WDF) d`l (DL) (b) The names of the process parameters of transistors are listed below: VFB flat-band voltage o|S surface inversion potential K1 body effect coefficient K2 drain/source depletion charge sharing coefficient n0 zero-bias drain-induced barrier lowering coefficient uZ zero-bias mobility U0Z zero-bias transverse-field mobility degradation coefficient U1Z zero-bias velocity saturation coefficient -5- uZB sensitivity of mobility to the substrate bias at Vds=0 nB sensitivity of drain-induced barrier lowering effect to the substrate bias nD sensitivity of drain-induced barrier lowering effect to the drain bias, at Vds= Vdd U0B sensitivity of transverse-field mobility degradation effect to the substrate bias U1B sensitivity of velocity saturation effect to the substrate bias uS mobility at zero substrate bias and at Vds=Vdd uSB sensitivity of mobility to the substrate bias at Vds=Vdd uSD sensitivity of mobility to the drain bias at Vds=Vdd U1D sensitivity of velocity saturation effect to the drain bias, at Vds= Vdd Tox gate-oxide thickness Temp temperature at which the process parameters are measured Vdd measurement bias range N0 zero-bias subthreshold slope coefficient NB sensitivity of subthrehold slope to the substrate bias ND sensitivity of subthrehold slope to the drain bias CGDO gate-drain overlap capacitance per meter channel width CGSO gate-source overlap capacitance per meter channel width CGBO gate-bulk overlap capacitance per meter channel length XPART gate-oxide capacitance model flag Note: XPART= 0, 0.5, and 1 selects the 40/60, 50/50, and 0/100 channel-charge partitioning methods, respectively. -------------------------------------------------------------- (c) The names of the process parameters of diffusion layers are listed below: sheet resistance/square Rsh O_/square zero-bias bulk junction bottom capacitance/unit area Cj F/m**2 zero-bias bulk junction sidewall capacitance/unit length Cjw F/m bulk junction saturation current/unit area Ijs A/m**2 bulk junction bottom potential Pj V bulk junction sidewall potential Pjw V bulk junction bottom grading coefficient Mj - bulk junction sidewall grading coefficient Mjw - default width of the layer Wdf m average reduction of size due to side etching or mask compensation d`s m ----------------------------------------------------------- (d) The names of the process parameters of poly and metal layers are listed as following: -6- sheet resistance/square Rsh O_/square capacitance/unit area Cj F/m**2 edge capacitance/unit length Cjw F/m default width of the layer Wdf m average variation of size due to side etching or mask compensation d`l m -7- 6. Examples (a) The following is an example of a process file. The lines starting with an asterisk (*) are used as comments. The MOSIS convention is that NM1 is for NMOS transistors, PM1 is for PMOS transistors, DU1 is for N+ diffusion, and DU2 is for P+ diffusion. NM1 PM1 PY1 ML1 ML2 DU1 DU2 * * PROCESS = GECM1 * RUN = m57r * WAFER = 11 * OPERATOR = David & Ming * DATE = 01/15/86 * NMOS model * -8.27348E-01, 1.42207E-01, 3.48523E-02 7.87811E-01, 0.00000E+00, 0.00000E+00 9.01356E-01, -1.96192E-01, 1.89222E-02 4.83095E-02, -4.10812E-02, -2.21153E-02 2.11768E-03, 3.04656E-04, -1.14155E-03 4.93528E+02, 5.39503E-02, 4.54432E-01 5.81155E-02, 4.95498E-02, -1.96838E-02 -5.88405E-02, 6.06713E-01, 4.88790E-03 9.22649E+00, -8.66150E+00, 9.55036E+00 -7.95688E-04, 2.67366E-03, 3.88974E-03 2.14262E-03, -7.19261E-04, -3.56119E-03 2.05529E-03, -3.66841E-03, 1.86866E-03 -1.64733E-02, -3.63561E-03, 3.59209E-02 4.84793E+02, 3.14763E+02, -3.91874E+01 -4.21265E+00, -7.97847E+00, 3.50692E+01 -5.83990E+00, 6.64867E+01, -1.99620E+00 -1.44106E-02, 8.14508E-02, 7.56591E-04 2.30000E-02, 2.30000E+01, 5.00000E+00 5.04000E-10, 5.04000E-10, 1.91000E-09 1.00000E+00, 0.00000E+00, 0.00000E+00 1.00000E+00, 0.00000E+00, 0.00000E+00 0.00000E+00, 0.00000E+00, 0.00000E+00 0.00000E+00, 0.00000E+00, 0.00000E+00 * * PMOS model * -5.63441E-01, -1.06809E-01, 1.32967E-01 7.46390E-01, 0.00000E+00, 0.00000E+00 6.57533E-01, 1.94464E-01, -1.60925E-01 -2.55036E-03, 1.14752E-01, -8.78447E-02 -5.59772E-03, 2.50199E-02, -5.66587E-04 1.73854E+02, 2.72457E-01, 6.57818E-01 1.26943E-01, 4.25293E-02, -4.31672E-02 -1.00718E-02, 1.50900E-01, -1.00228E-02 1.03128E+01, -3.94500E+00, 1.87986E+00 1.55874E-03, 4.80364E-03, -1.45355E-03 4.20214E-04, -2.05447E-03, -7.44369E-04 -8- 1.00044E-02, -4.43607E-03, 1.05796E-03 -5.64102E-04, 1.97407E-03, 6.65336E-04 1.77550E+02, 1.02937E+02, -2.94207E+01 8.73183E+00, 1.51499E+00, 9.06178E-01 1.11851E+00, 9.75265E+00, -1.88238E+00 -4.70098E-05, 9.43069E-04, -9.19946E-05 2.30000E-02, 2.30000E+01, 5.00000E+00 1.00000E-09, 1.00000E-09, 1.91000E-09 1.00000E+00, 0.00000E+00, 0.00000E+00 1.00000E+00, 0.00000E+00, 0.00000E+00 0.00000E+00, 0.00000E+00, 0.00000E+00 0.00000E+00, 0.00000E+00, 0.00000E+00 * * poly layer * 65.0, 7.20E-005, 0, 0, 0 0, 0, 0, 0, 0 * * metal layer 1 * 0.20, 4.30E-005, 0, 0, 0 0, 0, 0, 0, 0 * * metal layer 2 top metal * 0.10, 2.50E-005, 0, 0, 0 0, 0, 0, 0, 0 * * n+ diffusion layer * 80.0, 7.00E-004, 4.20E-010, 1.00E-008, 0.70 0.80, 0.50, 0.33, 0, 0 * * p+ diffusion layer * 140.0, 4.00E-004, 2.4E-010, 1.00E-008, 0.70 0.80, 0.50, 0.33, 0, 0 (b) The following deck determines the transient charac- teristics of a resistive load inverter with a capacitor con- nected at the output node. SAMPLE CMOS INVERTER VCC 1 0 5 SMN1 5 4 0 2 GECM1_NM1_DU1 W=3.8U L=1.2U SMP1 1 4 5 3 GECM1_PM1_DU2 W=2.5U L=1.2U VSU 3 0 DC 5 VWE 2 0 DC 0 VIN 4 0 PWL (0 5 5N 5N 10N 5 20N 0) -9- C1 5 0 50FF .OPTIONS RELTOL=1E-5 CHGTOL=1E-15 .TRAN 0.5N 20N .PRINT TRAN V(5) .PLOT TRAN V(5) .PROCESS GECM1 FILENAME=M57R .WIDTH OUT=80 .END Updated 1 June 1988