Table of Contents 1. Introduction 2. Scalable CMOS/Bulk 3. 3 Micron P-Well CMOS/Bulk 4. Electrical and SPICE Parameters 5. Geometry Layers ******************************************************************************* 1. CMOS/Bulk 1.1. Introduction MOSIS works with CMOS/Bulk fabricators capable of supporting 3.0, 2.0, 1.6, and 1.2 micron (feature size) double-metal technologies. The technologies are based upon two sets of design rules. The first set of scalable and generic design rules are for 3.0, 2.0, 1.6, and 1.2 micron double-metal (P well, N well, OR twin tub) processes. The second, nonscalable set is ONLY for 3.0 micron P well (double metal). Magic technology files are available from MOSIS for scalable and nonscalable CMOS. These files control design rule checking and map the Magic layers to or from GDSII or CIF layers. 2. Scalable CMOS/Bulk MOSIS offers a scalable CMOS (SCMOS) process with a second level of metal for interconnection. The main advantage of this technology is that it is scalable from 3.0 to 1.2 microns, since the same set of design rules covers all four feature sizes. This means that a 3.0 micron layout can be fabricated at 2.0, 1.6, or 1.2 microns by scaling a large fraction of the layout instead of redesigning to a new set of design rules. Pads, of course, cannot be scaled. These design rules also handle P well, N well, or twin tub processes. 2.1 CMOS with Capacitor Option To satisfy the requirements of analog designers, the MOSIS Service has developed a vendor-base capable of supporting a capacitor option, SC*E. BiCMOS and CCD options for CMOS processing are in development. Designers can use the MOSIS scalable set of design rules or the fabricator's own set of rules for these new options. 2.2. Magic Technology Files ---------------------------------------------------------------------- | | | | | The MOSIS version of the Magic technology files for SCMOS is | | frequently updated. WE RECOMMEND THAT YOU OBTAIN | | THIS FILE THROUGH MOSIS DIRECTLY. | | | | | ---------------------------------------------------------------------- To obtain this file,send an online request message in the following format to MOSIS@MOSIS.EDU: REQUEST: INFO TOPIC: SCMOS.Tech REQUEST: END 2.3 Submitting your Project to MOSIS Specify the technology and lambda in the NEW-PROJECT request for your project. The various SCMOS technologies are explained below (double poly is specified as SCPE, SCNE, SCEE and SCGE). TECHNOLOGY: SCP - P well processes (must include P well and P select layers). TECHNOLOGY: SCN - N well processes (must include N well, N select, or P select layers). TECHNOLOGY: SCE - P well or N well, processes (must include both wells and selects). MOSIS ignores N well and N select for a P well run and ignores P well and P select for a N well run. TECHNOLOGY: SCG - Generic Well, (must include a well and a select). MOSIS converts the well and select layers to P well and P select for P well processes and N well and N select for N well processes. TECHNOLOGY: SC*E - Adding E to SC*, e.g., SCPE, specifies the double poly process. 2.4. Specifying Lambda The desired value of lambda must also be specified. Note that this is NOT necessarily the grid size used by your CAD system. - LAMBDA: 1.5 for 3.0 micron feature size runs - LAMBDA: 1.0 for 2.0 micron feature size runs - LAMBDA: 0.8 for 1.6 micron feature size runs - LAMBDA: 0.6 for 1.2 micron feature size runs Please note the 1.6 and 1.2 micron runs are currently offered on a limited schedule. Please use the following to obtain the latest MOSIS fabrication schedule: REQUEST: INFORMATION TOPIC: SCHEDULE REQUEST: END 3.0 P-well CMOS/Bulk (3.0 micron) MOSIS supports a CMOS/Bulk process with a second layer of metal (CBPM) for interconnection. 3.1. Magic Technology Files --------------------------------------------------------------------- | | | | | The MOSIS version of the Magic technology files for CMOS is | | frequently updated. WE RECOMMEND THAT YOU OBTAIN | | THIS FILE THROUGH MOSIS DIRECTLY. | | | | | --------------------------------------------------------------------- To obtain this file send an online REQUEST message in the following format to MOSIS@MOSIS.EDU. REQUEST: INFO TOPIC: CBPM3u.Tech REQUEST: END Please be sure to specify the technology desired in the NEW-PROJECT request as follows: TECHNOLOGY: CBPM LAMBDA: 1.5 for 3.0 micron feature size runs Projects submitted for fabrication in the CBPM technology which contain no second metal or via features will be rejected at the CHECK_PROJ step (when your CIF is checked). 4.0 ELECTRICAL AND SPICE PARAMETERS MOSIS places its own test structures on each wafer and checks these structures on its tester. These results are used to confirm that each accepted wafer meets both the fabricator's electrical parameter specifications and MOSIS' specifications. MOSIS then generates SPICE Level 2 and/or BSIM model parameters for each run from these measurements. Sample SPICE Level 2 decks and BSIM are available as well as SPICE decks which are derived for each 3.0 and 2.0 micron fabrication run and BSIM decks derived for each 2.0, 1.6, and 1.2 micron run. Following is a list of available TOPIC files. You may request any number of filenames that fit on one line, separated by commas. Be sure to use the underscore punctuation as it appears in filenames and send your message to MOSIS@MOSIS.EDU. REQUEST: INFO TOPIC: VENDOR_SPECS, VENDOR_PRM REQUEST: END ******************************************************************************* Available TOPIC files: VENDOR_SPECS Vendor electrical specifications for all MOSIS 3.0, 2.0, 1.6 and 1.2 micron CMOS double metal vendors. VENDOR_PRM MOSIS measured parameters including electrical characterisics and SPICE (LEVEL 2 and/or BSIM) model decks. MOSIS_16UMBSIM MOSIS 1.6um fast/slow SPICE BSIM. MOSIS_2UMSPICE MOSIS 2um corner SPICE LEVEL 2. MOSIS_3UMSPICE MOSIS 3um corner SPICE LEVEL 2. MOSIS-provided SPICE model parameters (Level 2) are obtained from transistor DC curve fitting using a parameter optimizer and measurements from selected test structures. The optimizer uses the measured I-V data from fabricated transistors to obtain the SPICE model parameters. Each set of SPICE parameters is used to simulate a set of inverters as well as a ring oscillator. These circuits are fabricated as part of the MOSIS Process Monitor. The simulation of the test circuits is compared with the physical test circuits on the Process Monitor and the results are accurate to within 10 to 20 percent of measured performance. 5.0 Geometry Layers The charts below list the CIF and GDSII layer names that MOSIS accepts. In all technologies, CIF layer XP specifies boxes (NOT polygons) that designate bonding pad sizes and locations. See Chapter 9 (Section 9.3.6) for details. GDS users should note that only the layers listed in these charts are actual GDSII layers. All other layers are treated as comments (i.e., read but ignored); this has been indicated in the charts with an asterisk. Technology CIF GDSII CBPM P well, double level metal with MOSIS 3.0u rules. CW (1) P WELL CD (3) ACTIVE CP (4) POLY CS (5) P+ SELECT CC (7) CONTACT CM (8) METAL1 CV (13) VIA CQ (14) METAL2 CG (9) GLASS CX (*) COMMENT (non-fabricated geometry) SCP P well, double level metal with MOSIS scalable rules. CWP (41) P WELL CAA (43) ACTIVE CSP (44) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) SCN N well, double level metal with MOSIS scalable rules. CWN (42) N WELL CAA (43) ACTIVE CSN (45) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) Technology CIF GDSII SCG Generic wells, double level metal with MOSIS scalable rules. CWG (53) WELL CAA (43) ACTIVE CSG (54) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) SCE Both wells, double level metal with MOSIS scalable rules. CWP (41) P WELL CWN (42) WELL CAA (43) ACTIVE CSP (44) SELECT CSN (45) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) SC*E Add the following two layers to the scalable technologies listed above. CEL (56) ELECTRODE CCE (55) CONTACT TO ELECTRODE LAYOUT GRIDS When you are submitting CIF to MOSIS, your design layout should be in centimicrons; NEVER submit a design in lambda or centilambda. SCMOS RULES - 3.0, 2.0, 1.6, and 1.2 Micron If you are using the MOSIS Scalable and Generic CMOS Design Rules (Revision 6), you must stay on a lambda grid for all layers and a half lambda grid for metals. NONSCALABLE RULES, 3.0 MICRON The MOSIS 3.0 micron P well CMOS Design Rules (Revision 2) require a one micron grid. FABRICATOR'S RULES Fabricator's rules are variable; check the fabricator's specifications.