13.5. MOSIS Glossary This glossary contains a list of terms and their descriptions as they are used by the MOSIS Service. Some of these terms are standard in the semiconductor industry, while others are specific to MOSIS. Technology names and descriptions (e.g., SCN) can be found in the CMOS chapter. ASIC An acronym for Application Specific Integrated Circuit, e.g., a custom or semi-custom part. BSIM An acronym for "Berkeley Short Channel IGFET Model". A simple and accurate short-channel MOS transistor model, developed at Berkeley, which can be used with SPICE simulation. Bonding fingers Another term for package pins. CHECK_PROJ A step run by MOSIS upon receipt of a GDSII or CIF file to check the validity of the file (syntax, layer names, size, etc.). Projects that do not pass CHECK_PROJ are not accepted. MOSIS does not do any design rule check on submitted files. CIF-CHECKSUM A CIF-specific checksum program designed to ensure the integrity of a CIF file sent from your system to MOSIS. The CIF checksum computed by your system accompanies the CIF file and is compared to the checksum computed by MOSIS on the received file. CIF (Caltech Intermediate Form). A readable text format with specific constructs for describing VLSI circuit(s) layouts. CMOS3 Cell Library A standard cell library developed by a department of the U.S. government and available from MOSIS. DAR An acronym for Device Acknowledgment Receipt. An acknowledgment of receipt of parts from your MOSIS Liaison. Used by MOSIS in tracking and verification procedures. DARPA The Defense Advanced Research Projects Agency provides funding for the MOSIS Service. DIP Dual In-line Package, a rectangular package for integrated circuits with leads along two parallel sides. MOSIS uses 0.6" wide, ceramic, side-brazed packages with 0.1" pin spacing. Downbond Synonymous with substrate connection; a bonding wire from a package bonding finger to the package cavity. Since the die attach used to affix the chip to the cavity is electrically conductive, this connects that bonding finger (and the lead it is connected to) to the substrate of the chip through the package cavity. Electronic mail A text message (mail) sent from one user to another via computer networks. FTP An acronym for File Transfer Program. A software program that allows users to transfer files between computers on the Internet. Fusion Service A placement and routing service; refers to the automatic placement and wiring of layout cells, which yields a totally integrated, or "fused" layout. Gateway A computer that connects networks together. Header Electronic mail messages are divided into text and headers. The header contains address information, e.g., who and where the message is from, and who and where the message is going to; it also includes the date and subject of the message. Lambda: An abstract unit for design layout measurement, which is defined in relation to the fabricator's resolution of the chip-making process. Lambda has different values for different feature size processes and is usually one-half the feature size. Leaf cells A layout with its ports of communication. (See Fusion Service.) Mail relay A host that forwards electronic mail from one network to another. MOSIS Command Language MOSIS automatic message software which allows online users to request information and run status from MOSIS. MOSIS Command Language request A message sent to MOSIS in a "Request" format. All such messages are answered by the automatic message service except "Attention" messages, which are received and answered by the MOSIS staff. NSF The National Science Foundation provides funding for the MOSIS Service. Network A group of connected machines that can transmit information among the different hosts sharing a protocol family, e.g., the Internet uses the IP/TCP protocol suite. Network path The sequence of machine names forming an address path for information flow to and from hosts on other networks. Pad The bonding pad (the square of metal under an overglass opening that the bonding wire is attached to) and the buffer circuitry for input and/or output signals. Payload area The area designated for users' projects on MOSIS' standard chip sizes. MOSIS reserves area for the scribe lanes and the MOSIS labeling strip. PGA Pin Grid Array. A square package for integrated circuits, with leads in a regular grid on the bottom of the package. MOSIS uses cavity-up ceramic packages with 0.1" lead spacing. (Cavity-up means the cavity for the chip is on the top of the package, as with DIPs.) PM Process Monitor. A set of MOSIS' parametric and functional test structures used in wafer lot acceptance. Postmaster The name of the user on your machine who handles undeliverable mail. Probe card A printed circuit board with metal pins that protrude to touch the bonding/probe pads of the DUT (Device Under Test) so that signals can be sent to and received from the part. Project-ID The first request (other than for information) a user sends to MOSIS is for a proposed project. MOSIS replies by assigning a Project-ID (e.g., 12345), which must be used in all future requests pertaining to that project. Protocol A set of communication procedures and formats used between computers on a network (e.g., the IP/TCP suite of protocols on the Internet). Remote network A network that is not directly connected to your machine and therefore must be accessed via a "mail relay". Routing Wiring that causes cells to communicate with one another. Run An aggregation of projects of a particular technology scheduled to be fabricated on the same wafer is referred to as a "run". Site A computer system on a network is called a "site" (also a "node" or "host"). SPICE model parameters These parameters are used to describe the characteristics of a fabrication process (e.g., transistor thresholds). SPICE uses them to determine the behavior of elements as part of a simulated circuit. Standard cells Modular layouts for implementing "common" or "standard" functions. The layouts are usually of a fixed height with fixed power connections; this facilitates automated grouping into rows with routing between the rows. Standard Frame A set of bonding pad locations and their minimum sizes, located around the periphery of a rectangle of fixed size. Substrate See Downbond. TDL Test Description Language; a readable text file with specific constructs for describing test vectors, optional timing, and voltage levels. Test vector The set of voltage levels (0, 1, etc.) to be applied to or received from the DUT (Device Under Test) across the set of DUT pins or pads; also called a test pattern. Your network The group of machines that communicate with your machine using a shared protocol. This group can communicate with other networks via a mail relay.