DIRECTORY OF MOSIS CELL LIBRARIES, current to 11-10-89 OBTAINING LIBRARY FILES To obtain Cell Library files, type your request in the following format: REQUEST: LIBRARY LIBRARY: FILE: , is one of the MOSIS Libraries listed below, and is the name of a file residing in the indicated cell library. You may obtain a list of a library's files by simply requesting: REQUEST: LIBRARY LIBRARY: SCP30_PADS (for example) ************************* SUPPORTED LIBRARIES *************************** LIBRARY FEATURE MM-DD-YY MM-DD-YY NAME TECH SIZE DESCRIPTION CREATED MODIFIED ------------------------------------------------------------------------- CMOS3REL6_1 CBPM 3.0 Mosis Standard Cells 02-19-89 02-19-89 CMOSN_20A NSCT 1.2,2.0 Mosis Standard Cells 11-14-89 11-14-89 *(CMOSN_20A is available only on tape after signed license agreement & $225) ************************ UNSUPPORTED LIBRARIES ************************** LIBRARY FEATURE MM-DD-YY MM-DD-YY NAME TECH SIZE DESCRIPTION CREATED MODIFIED ------------------------------------------------------------------------- SCP30_PADS SCP 3.0 Mosis NSF(TinyChip)Pads 12-23-86 11-10-89 *(formerly called NSF_SCP3U_PADS) SCN20_PADS SCN 2.0 Mosis TinyChip Pads 07-05-88 11-10-89 SCP20_PADS SCP 2.0 Mosis TinyChip Pads 03-08-89 11-10-89 CIT_SCN20_PADS SCN 2.0 CIT(Seitz)TinyChip Pads 07-05-88 11-10-89 SCN16_PADS SCN 1.6 Mosis TinyChip Pads 11-22-88 11-10-89 SCN12_PADS SCN 1.2 Mosis TinyChip Pads 07-13-89 11-10-89 OVERSIZE_SCN12_PADS SCN 1.2 Higher current Pads 11-15-89 11-15-89 MENTORREL4 CBPM 3.0 Mentor Std. Cell Pads 12-23-86 04-28-88 *(references library CMOS3REL4) MIT_CBPM30_PADS CBPM 3.0 MIT Pad Cells (2 Metal) 12-23-86 11-10-89 MIT_CBP30_PADS CBP 3.0 MIT Pad Cells (1 Metal) 12-23-86 11-10-89 MIT_SCP30_PADS SCP 3.0 Mosis MIT Pad Cells 12-23-86 11-10-89 *************************** INFORMATION ONLY **************************** LIBRARY FEATURE MM-DD-YY MM-DD-YY NAME TECH SIZE DESCRIPTION CREATED MODIFIED ------------------------------------------------------------------------- STD_FRAMES none 0.0 Standard Frame Pad Locs 12-23-86 08-17-87 Notes ******************************************************************** KEY TO THE ABOVE TABLE: LIBRARY NAME is the name of the library. Note that some libraries, such as ones holding cell revisions, reference prior libraries for the remainder of the cell set. TECH gives the technology name of the cells in the library. Most technologies are NOT compatible with each other, and no checking of incompatible technologies is made (other than the usual CIF rejection of unknown layer names). FEATURE SIZE gives the minimum poly gate width of the smallest transistor (equal to twice 'LAMBDA'). DESCRIPTION gives the source of the cells, their overall nature, and any special library or technology features, such as a non-standard number of METAL layers, for example. MM-DD-YY CREATED gives the library installation date (month, day, and year. MM-DD-YY MODIFIED gives the date of any changes to the library. Note, however, that cells of the library never change -- rather, a new library is installed, supplying any cell updates, and referencing the old library as a subset. So, although no changes are made to the original library's cells, the MM-DD-YY MODIFIED date alerts users to check the original library's documentation for update information. NOTE ON REMARKS: Remarks files contain user-contributed reports on library cells, and are accessed by the LIBRARY file request in the MOSIS mail service: REQUEST: LIBRARY LIBRARY: FILE: .REM SPECIAL NOTE ON PAD LIBRARIES: PAD CELLS are not generally scalable, because of absolute pad size restrictions and the electrical differences between linear vrs. area scaling. Thus, scalable libraries are usually broken into two libraries, one containing the non-pad cells and one containing pads. @"MINFOVIS:LIBINF.DOC ; Built: 15-NOV-1989 14:38 (JWS) @"mosis_data:[cell_libraries]libraries.doc Following is a brief summary of the library cells and documentation files available from MOSIS. Each library contains a documentation file (.DOC) and a .CIF file (.CIF) which includes all the cells of the library. In addition, some libraries contain individual .CIF files for each cell (.CIF), and possibly a Remarks file (.REM), which provides usage notes for the library. Other (NON ELECTRICALLY-MAILABLE) formats such as Calma GDS2 exist for some libraries: contact MOSIS for information including a possible tape charge fee. To obtain any on-line file, ask for it in a LIBRARY request to MOSIS: REQUEST: LIBRARY LIBRARY: FILE: Technology Description -------------------------------------------------------- CMOS3REL6_1 CBPM 3.0 Mosis Standard Cells The CMOS3REL6_1 Library contains 131 cells including SSI logic cells, MSI Logic cells (compositions of SSI cells), Stackable Shift-register, Fiduciary, and Pad I/O cells. The cells are in the MOSIS CBPM technology, a 3 micron CMOS/Bulk P-well double metal process. Chip designs generated using this library can be fabricated on any MOSIS CBPM wafer fabrication run. CMOS3REL6_1 is a SUPPORTED Library. 6430 CMOS3REL6_1.DOC;5 1734740 CMOS3REL6_1.CIF;1 14094 9720.CIF;1 13500 9710.CIF;1 17258 9680.CIF;1 17374 9670.CIF;1 5494 9660.CIF;1 5554 9650.CIF;1 426 9620.CIF;1 7972 9540.CIF;1 7968 9530.CIF;1 8558 9470.CIF;1 9456 9460.CIF;1 174 9320.CIF;1 8034 9260.CIF;1 8418 9250.CIF;1 7136 9160.CIF;1 7704 9150.CIF;1 3616 9120.CIF;1 3206 9110.CIF;1 100 8690.CIF;1 100 8680.CIF;1 144 8670.CIF;1 662 8660.CIF;1 134 8640.CIF;1 298 8630.CIF;1 1750 8220.CIF;1 2680 8210.CIF;1 2914 8200.CIF;1 396 8140.CIF;1 218 8130.CIF;1 428 8090.CIF;1 356 8080.CIF;1 426 8070.CIF;1 234 8050.CIF;1 378 8040.CIF;1 290 8030.CIF;1 170 8010.CIF;1 96130 4790.CIF;1 61490 4780.CIF;1 21138 4770.CIF;1 14168 4760.CIF;1 5792 4720.CIF;1 6738 4710.CIF;1 50914 4700.CIF;1 192 4640.CIF;1 670 4630.CIF;1 168 4620.CIF;1 216 4610.CIF;1 82460 4590.CIF;1 3924 4580.CIF;1 35240 4570.CIF;1 4542 4560.CIF;1 130638 4490.CIF;1 8552 4480.CIF;1 59266 4470.CIF;1 358 4460.CIF;1 69236 4450.CIF;1 632 4440.CIF;1 34418 4430.CIF;1 16798 4420.CIF;1 632 4410.CIF;1 35860 4400.CIF;1 37982 4370.CIF;1 56784 4360.CIF;1 5910 4350.CIF;1 4660 4340.CIF;1 3712 4330.CIF;1 2494 4320.CIF;1 72824 4310.CIF;1 69826 4300.CIF;1 2962 4230.CIF;1 21768 4220.CIF;1 17816 4210.CIF;1 116094 4200.CIF;1 632 4130.CIF;1 18192 4120.CIF;1 21418 4110.CIF;1 102230 4100.CIF;1 44750 4090.CIF;1 3666 4080.CIF;1 2398 4070.CIF;1 18798 4050.CIF;1 32964 4020.CIF;1 6796 4010.CIF;1 19000 4000.CIF;1 326 2940.CIF;1 404 2930.CIF;1 2508 2920.CIF;1 6112 2910.CIF;1 3798 2900.CIF;1 2624 2350.CIF;1 3412 2310.CIF;1 4918 1970.CIF;1 5078 1930.CIF;1 9218 1910.CIF;1 3782 1870.CIF;1 8092 1850.CIF;1 5484 1830.CIF;1 6676 1810.CIF;1 2572 1770.CIF;1 2094 1760.CIF;1 2730 1740.CIF;1 2636 1680.CIF;1 2346 1670.CIF;1 2166 1660.CIF;1 2120 1620.CIF;1 1770 1610.CIF;1 7628 1580.CIF;1 6758 1570.CIF;1 3082 1560.CIF;1 2086 1550.CIF;1 1024 1540.CIF;1 5110 1530.CIF;1 3308 1520.CIF;1 3256 1510.CIF;1 8984 1480.CIF;1 644 1440.CIF;1 636 1430.CIF;1 2598 1420.CIF;1 3000 1410.CIF;1 2454 1370.CIF;1 3684 1350.CIF;1 3622 1340.CIF;1 1788 1320.CIF;1 1282 1310.CIF;1 1866 1230.CIF;1 1470 1220.CIF;1 2084 1140.CIF;1 2114 1130.CIF;1 1608 1120.CIF;1 2316 1100.CIF;1 SCP30_PADS SCP 3.0 Mosis NSF(TinyChip)Pads This 3 micron SCMOS (P-well) TINYchip pads set was designed with the MOSIS Scalable CMOS design rules at a lambda of 1.5 microns. They should be submitted as a MOSIS Scalable CMOS P-Well (SCP) project. All pads were laid out on a lambda grid and are designed for the 28PC23x34 standard frame. This set contains six pads, including I/O, IN, Out, Vdd, ground, and blank pad cells, and two auxiliary cells, a spacer and corner cell. 2252 VDD.CIF;1 664 SPACER.CIF;1 5202 SCP30_PADS.DOC;2 161504 SCP30_PADS.CIF;1 34234 OUT.CIF;1 34208 IO.CIF;1 34234 IN.CIF;1 2478 GND.CIF;1 2312 CORNER.CIF;1 4826 BLANK.CIF;1 46382 28PC23X34_STUFFED.CIF;2 SCN20_PADS SCN 2.0 Mosis TinyChip Pads This 2 micron SCN (N-well) TinyChip pads set was designed with the MOSIS scalable CMOS design rules at a lambda of 1 micron. All pads are laid out on a lambda grid and are designed to be used with the 40PC22X22 Standard Frame. When submitting a project to MOSIS using this pad set, you must specify the technology as 'SCN' or 'SCE'. This set contains six pad frame cells, I/O, IN, OUT, Vdd, Ground, and a blank pad, plus two corner pad cells for supplying Vdd and Ground to the pad ring. Also, there is a separate complete pad frame cell for analog uses: its pads have no buffers -- just static voltage protection diodes. 4436 VDD.CIF;1 4956 SCN20_PADS.DOC;1 96782 SCN20_PADS.CIF;1 25092 OUT.CIF;1 25092 IO.CIF;1 25178 IN.CIF;1 4856 GND.CIF;1 4312 CV.CIF;1 3346 CG.CIF;1 4456 BLANK.CIF;1 14452 ANALOG.CIF;1 32964 40PC22X22_STUFFED_ANALOG.CIF;1 42478 40PC22X22_STUFFED.CIF;1 SCP20_PADS SCP 2.0 Mosis TinyChip Pads This 2 micron SCP (P-well) TinyChip pads set was designed with the MOSIS scalable CMOS design rules at a lambda of 1 micron. All pads are laid out on a lambda grid and are designed to be used with the 40PC22X22 Standard Frame. When submitting a project to MOSIS using this pad set, you must specify the technology as 'SCP' or 'SCE'. This set contains six pad frame cells, I/O, IN, OUT, Vdd, Ground, and a blank pad, plus two corner pad cells for supplying Vdd and Ground to the pad ring. Also, there is a separate complete pad frame cell for analog uses: its pads have no buffers -- just static voltage protection diodes. 6718 VDD.CIF;1 4620 SCP20_PADS.DOC;1 184010 SCP20_PADS.CIF;1 21488 OUT.CIF;1 21518 IO.CIF;1 21492 IN.CIF;1 6700 GND.CIF;1 3394 CV.CIF;1 2116 CG.CIF;1 7530 BLANK.CIF;1 16612 ANALOG.CIF;1 34998 40PC22X22_STUFFED_ANALOG.CIF;1 41444 40PC22X22_STUFFED.CIF;1 CIT_SCN20_PADS SCN 2.0 CIT(Seitz)TinyChip Pads This 2 micron SCN (N-well) TinyChip pads set was designed with MAGIC. When submitting a project to MOSIS using this pad set, you must specify the technology as 'SCN' or 'SCE'. This set contains seven cells, GNDPAD, INPAD, NULPAD, OUTPAD, SCHMITTPAD, TRIPAD, and VDDPAD. MOSIS believes that these MAGIC .MAG files will read in without design rule violations under Rev6 of the SCMOS MAGIC technology file. 1704 VDDPAD.MAG;1 17078 TRIPAD.MAG;1 12470 SCHMITTPAD.MAG;1 16124 OUTPAD.MAG;1 4856 NULPAD.MAG;1 8032 INPAD.MAG;1 1484 GNDPAD.MAG;1 1224 CIT_SCN20_PADS.DOC;1 2250 40P22X22_STUFFED.MAG;1 SCN16_PADS SCN 1.6 Mosis TinyChip Pads This 1.6 micron SCN (N-well) TinyChip pads set was designed with the MOSIS scalable CMOS design rules at a lambda of 0.8 micron. All pads are laid out on a lambda grid and are designed to be used with the 40PC22X22 Standard Frame. When submitting a project to MOSIS using this pad set, you must specify the technology as 'SCN' or 'SCE'. This set contains six pad frame cells, I/O, IN, OUT, Vdd, Ground, and a blank pad, plus two corner pad cells for supplying Vdd and Ground to the pad ring. 5178 VDD.CIF;1 562 SCN16_PADS.DOC;1 118352 SCN16_PADS.CIF;1 31372 OUT.CIF;1 31456 IO.CIF;1 31436 IN.CIF;1 5012 GND.CIF;1 3534 CV_R.CIF;1 3412 CV.CIF;1 1196 CG_R.CIF;1 1220 CG.CIF;1 4518 BLANK.CIF;1 52052 40PC22X22_STUFFED.CIF;1 SCN12_PADS SCN 1.2 Mosis TinyChip Pads This 1.2 micron SCN (N-well) TinyChip pads set was designed with the MOSIS scalable CMOS design rules (rev 6) at a lambda of 0.6 micron. You should obtain the newest Magic technology (dated no earlier than 7/1/88) from MOSIS to use these pads. All pads are laid out on a lambda grid. When submitting a project to MOSIS using this pad set, you must specify the technology as 'SCN' or 'SCE' (if you wrote the CIF file with both wells), and set the LAMBDA to 0.6 MICRON. This set contains six pad frame cells, IO, IN, OUT, VDD, GND, and a BLANK pad, plus two corner pad cells for supplying Vdd and Ground to the pad ring. 7748 VDD.CIF;1 3220 TR.CIF;1 3294 TL.CIF;1 4838 SCN12_PADS.DOC;3 233422 SCN12_PADS.CIF;1 43776 OUT.CIF;1 43696 IO.CIF;1 43672 IN.CIF;1 7566 GND.CIF;1 2356 BR.CIF;1 7120 BLANK.CIF;1 2478 BL.CIF;1 70292 40PC19X19_STUFFED.CIF;1 OVERSIZE_SCN12_PADS SCN 1.2 Higher current Pads This 1.2 micron SCN (N-well) pads set was designed with the MOSIS scalable CMOS design rules (rev 6) at a lambda of 0.6 micron. These are higher current (and larger size) versions of some of the pads from the standard SCN12_PADS pad library. However, these pads won't fit into the TinyChip pad frame, and are essentially uncharacterized, but are known to be functional. 20724 VDD.CIF;1 20472 TL.CIF;1 1076 SPACER.CIF;1 930 OVERSIZE_SCN12_PADS.DOC;4 53702 OUT.CIF;1 56080 INB.CIF;1 45692 IN.CIF;1 22246 GND.CIF;1 20550 BLANK.CIF;1 MENTORREL4 CBPM 3.0 Mentor Std. Cell Pads The MENTORREL4 Library contains 40 pad cells which are modifications to the pad cells of the CMOS3REL4 Standard Cell Library. Modifications include cell reorientation and power bus widening. This Library was provided by Mentor Graphics Corporation for its Design Kit support of the MOSIS CMOS 3 standard cell technology. 256 VSS20R.CIF;2 244 VSS20.CIF;2 338 VSS10R.CIF;2 326 VSS10.CIF;2 338 VDD20R.CIF;2 326 VDD20.CIF;2 256 VDD10R.CIF;2 244 VDD10.CIF;2 400302 MENTORREL4_FLAT.CIF;1 396 MENTORREL4.REM;2 2740 MENTORREL4.DOC;10 90 MENTORREL4.DEF;3 308618 MENTORREL4.CIF;2 15320 9720MR.CIF;2 14306 9720M.CIF;2 14618 9710MR.CIF;2 13648 9710M.CIF;2 18818 9680MR.CIF;2 17550 9680M.CIF;2 18924 9670MR.CIF;2 17544 9670M.CIF;2 6170 9660MR.CIF;2 5610 9660M.CIF;2 6198 9650MR.CIF;2 5680 9650M.CIF;2 8790 9540MR.CIF;2 8092 9540M.CIF;2 8794 9530MR.CIF;2 8178 9530M.CIF;2 9532 9470MR.CIF;2 8740 9470M.CIF;2 10462 9460MR.CIF;2 9648 9460M.CIF;2 8676 9240MR.CIF;2 7960 9240M.CIF;2 8710 9230MR.CIF;2 8016 9230M.CIF;2 8018 9160MR.CIF;2 7286 9160M.CIF;2 8626 9150MR.CIF;2 7890 9150M.CIF;2 3938 9120MR.CIF;2 3666 9120M.CIF;2 3576 9110MR.CIF;2 3262 9110M.CIF;2 MIT_CBPM30_PADS CBPM 3.0 MIT Pad Cells (2 Metal) These pads are intended for fabrication under the MOSIS 3 micron CMOS double metal process "CBPM" and do use second metal. They were layed out on a 1 micron grid. These pads were designed by Paul Bassett. Bill Ackerman has worked on making their layout cleaner and more regular, developing the library of padframes and doing some testing of the pads. There are 12 pads in the set, including pad1bin-ttl, pad1out-ttl, pad1vdd2, pad1gnd2, pad1ts, pad1space, pad1out, pad1bin, pad1gnd, pad1vdd, pad1in, pad1 1964 PAD1VDD2.CIF;1 1994 PAD1VDD.CIF;1 45756 PAD1TS.CIF;1 1916 PAD1SPACE.CIF;1 45246 PAD1OUT_TTL.CIF;1 40960 PAD1OUT.CIF;1 5992 PAD1IN.CIF;1 1530 PAD1GND2.CIF;1 1532 PAD1GND.CIF;1 16298 PAD1BIN_TTL.CIF;1 21368 PAD1BIN.CIF;1 10204 MIT_CBPM30_PADS.DOC;1 62586 MIT_CBPM30_PADS.CIF;1 MIT_CBP30_PADS CBP 3.0 MIT Pad Cells (1 Metal) These pads are intended for fabrication under the MOSIS 3 micron CMOS process "CBP". They do not use second poly or second metal. They were layed out on a 1 micron grid. These pads were designed by Paul Bassett. Bill Ackerman has worked on making their layout cleaner and more regular, developing the library of padframes and doing some testing of the pads. The pads are divided into 3 groups. All of the pads in each group are compatible with the other members of its group but the groups are not compatible with each other due to power bus mismatches. Group1 contains pad1out, pad1in, pad1bin, pad1vdd, pad1gnd, pad1ts, pad1space, pad1bin-ttl, and pad1out-ttl. Group 2 contains pad2in, pad2bin, pad2bin-ttl, pad2gnd, pad2vdd, and pad2space. Group 3 contains pad3vdd, pad3in, pad3gnd, and pad3space. 1048 PAD1VDD.CIF;1 37642 PAD1TS.CIF;1 1024 PAD1SPACE.CIF;1 39284 PAD1OUT_TTL.CIF;1 33302 PAD1OUT.CIF;1 4504 PAD1IN.CIF;1 922 PAD1GND.CIF;1 14614 PAD1BIN_TTL.CIF;1 17716 PAD1BIN.CIF;1 10350 MIT_CBP30_PADS.DOC;1 75722 MIT_CBP30_PADS.CIF;1 MIT_SCP30_PADS SCP 3.0 Mosis MIT Pad Cells These pads were designed with the MOSIS scalable CMOS (SCMOS) design rules at lambda = 1.5 microns. They do use second metal and are intended for use on MOSIS SCP (scalable CMOS P-Well) 3.0 micron (feature size) projects. The pads were layed out on a 1 lambda grid. The orginial version of these pads were designed by Paul Bassett and Bill Ackerman at MIT using the MOSIS 3 micron (non-scalable) design rules. This pad set was modified from their Pad1 set. It contains 9 pad cells, including PadBlank, PadAnalog, PadGND, PadIO, PadIn, PadInTTL, PadOut, PadOutTTL, and PadVdd pads, and 2 auxiliary cells, a spacer and a corner cell. 320 PAD_SPACER.CIF;2 606 PAD_CORNER.CIF;2 2094 PADVDD.CIF;2 24064 PADOUT_TTL.CIF;2 18720 PADOUT.CIF;2 22836 PADIO.CIF;2 8334 PADIN_TTL.CIF;2 10030 PADIN.CIF;2 1000 PADGND.CIF;2 908 PADBLANK.CIF;2 2890 PADANALOG.CIF;2 6868 MIT_SCP30_PADS.DOC;1 91934 MIT_SCP30_PADS.CIF;1 STD_FRAMES none 0.0 Standard Frame Pad Locs The MOSIS service offers standard frames as an alternative to custom project frames where every project pad layout is unique. A standard project frame is a rectangular area of a fixed size and with a fixed set of bonding pad locations around the periphery of the rectangle. The circuitry in the remainder of the frame, the routing of pad connections, and the choice of pad types at each of the fixed locations are up to the user. Standard frames are available in six sizes and four different pad counts, for a total of eleven standard frames as listed in the documentation. 11984 STD_FRAMES.DOC;2 112 STANDARD_FRAMES.LIST;1 11598 STANDARD-FRAMES.INF;7 374 PARCBASIC.LIST;1 1140 PARCBASIC.CIF;1 2228 84P79X92.LIST;1 3418 84P79X92.CIF;1 2228 84P69X68.LIST;1 3418 84P69X68.CIF;1 1710 64P79X92.LIST;1 2846 64P79X92.CIF;1 1710 64P69X68.LIST;1 2850 64P69X68.CIF;1 1710 64P46X68.LIST;1 2846 64P46X68.CIF;1 1178 40PC22X22.LIST;3 5274 40PC22X22.CIF;1 1086 40P69X68.LIST;1 2126 40P69X68.CIF;1 1084 40P46X68.LIST;1 2126 40P46X68.CIF;1 1086 40P46X34.LIST;1 2126 40P46X34.CIF;1 854 28PC23X34.LIST;3 1708 28PC23X34.CIF;2 774 28P46X34.LIST;1 1764 28P46X34.CIF;1 928 28P23X34.LIST;3 1890 28P23X34.CIF;3