* THE LATEST CMOS SCALABLE RULES ARE DATED FEBRUARY 1988 - REVISION 6 * CIF files showing Revision 6 design rules may be obtained by sending this message to : REQUEST: INFORMATION TOPIC: SCRULES6 REQUEST: END Please note that the rules are NOW listed under SCRULES6_*.CIF (where * is from 1 to 19, not SCMOS*) for those who would like to request individual pages. Below is a listing of the individual pages. SCRULES6_1 ==> COVER_PAGE SCRULES6_2 ==> SUMMARY_PAGE SCRULES6_3 ==> LAYER_PAGE SCRULES6_4 ==> REQUIRED_LAYERS_PAGE SCRULES6_5 ==> INSTRUCTIONS_PAGE SCRULES6_6 ==> LAMBDA_PAGE SCRULES6_7 ==> VENDOR_PAGE SCRULES6_8 ==> WELL_PAGE SCRULES6_9 ==> ACTIVE_PAGE SCRULES6_10 ==> POLY_PAGE SCRULES6_11 ==> SELECT_PAGE SCRULES6_12 ==> SIMPLER_POLY_CONTACT_PAGE SCRULES6_13 ==> DENSER_POLY_CONTACT_PAGE SCRULES6_14 ==> SIMPLER_ACTIVE_CONTACT_PAGE SCRULES6_15 ==> DENSER_ACTIVE_CONTACT_PAGE SCRULES6_16 ==> METAL1_PAGE SCRULES6_17 ==> VIA_PAGE SCRULES6_18 ==> METAL2_PAGE SCRULES6_19 ==> GLASS_PAGE To receive information on the ELECTRODE (Second Poly) layer, request: REQUEST: INFORMATION TOPIC: SCRULES_ELECTRODE REQUEST: END --------------------------------------------------------------------------- RULE CHANGE HISTORY --------------------------------------------------------------------------- Rev6. 3/88 These changes will allow MOSIS to access a larger fabricator base for the feature sizes that we now support (lambda equal to 1.5, 1.0, and 0.8 microns) and new fabricators for yet smaller feature sizes (lambda equal to 0.6 microns). The changes also allow for the new 2 micron double poly and double metal process which will be available by late June 1988. Differences are as follows: 1. Minimum active width is now 3 as opposed to 2 lambda. 2. Minimum active overlap of poly is now 3 as opposed to 2 lambda. 3. Minimum well width is now 10 as opposed to 9 lambda. 4. Feature edges on lambda equal to or smaller than 1.0 micron runs must be on half lambda grids. Feature edges on lambda equal to 1.5 micron runs must be on a lambda grid except for metals which can be on a half lambda grid. 5. The electrode rules (second poly layer) are PRELIMINARY and are subject to change. --------------------------------------------------------------------------- Rev5. 9/86 Minimum well-width changed from 6 to 9 lambda (especially for 2 and 1.2 microns). Rule 1.1 Specification of both n+select (CSN) and p+select (CSP) for an N-well design were added. --------------------------------------------------------------------------- Rev4. 11/85 The miminum width and spacing of select features was added (2 lambda). Rule 4.4 The well width spacing changed from 6 to 9 lambda. Rule 1.2 --------------------------------------------------------------------------- Rev3. 9/23/85 The minimum via to via separation was changed from 2 to 3 lambda. A rule related to the minimum distance between a contact to active and a contact to poly was added. This minimum distance is 4 lambda. It was recommended that the minimum transistor width especially for two and 1.2 micron runs be kept at 3 lambda. It was recommended that for long runs ( > 10 microns) of parallel active and metal1 coincident poly and active edges be avoided and that the separation of those edges be kept at a minimum of 1 lambda. This recommendation applies only to 1.2 micron technologies. --------------------------------------------------------------------------- Rev2. 9/85 The rules related to the spacing between substrate and well contact actives to well edge were changed. The minimum spacing between these actives and the well edge was set to 3 lambda. --------------------------------------------------------------------------- Version #1 8/23/85 SCMOS1.CIF Scalable and generic CMOS/Bulk design rule through package (19 pages total) applicable to 3, 2, and SCMOS19.CIF 1.2 micron P- well and N- well CMOS technologies. ---------------------------------------------------------------------------