4. VLSI CAD Tools 4.1. Introduction There is a wide range of VLSI CAD tools that can be used with MOSIS; these have different capabilites, prices, and sources. Only a subset of these is discussed in this chapter; the first part covers commercial CAD tools and the second reviews available public domain tools. All ASIC geometry, designed on any of these or other similar CAD tools, is acceptable to MOSIS as long as the design layout is compatible with the sets of design rules that MOSIS supports and is within the range of MOSIS' electrical parameters. 4.2. Commercial VLSI CAD Tools for Use with MOSIS There are several commercial CAD companies that support the CMOS3 Cell Library distributed by MOSIS, e.g., Mentor Graphics. Chip designs generated using these CAD systems can be fabricated on any 3.0 micron CBPM MOSIS wafer run. If you are using any of these systems to do standard cell design, you have two alternatives in submitting your design to MOSIS, depending on whether you are designing in GDSII or CIF format. If you submit your design in GDSII, MOSIS will instantiate the library cells during preparation for fabrication. If you are designing in CIF, you need to order the cell library from MOSIS and add the cells yourself before submitting your design. 4.2.1. Circuit Simulation There are many commercial versions of SPICE (the circuit simulator) which provide better convergence and support, as well as handling larger circuits than regular SPICE. HSPICE is one of these; it is available from Meta-Software. 4.3. Public-Domain VLSI CAD Tools for Use with MOSIS 4.3.1. CMOS3 Cell Library This library, developed by a U.S. Government agency within the Department of Defense, can be ordered from MOSIS. It contains more than 130 cells, including both logic and I/O pad cells. The cells are designed to the MOSIS 3.0 micron CMOS/Bulk P well double metal (CBPM) nonscalable design rules. Chip designs generated using this library can be fabricated through MOSIS on any MOSIS CBPM wafer fabrication run. (For a description of this library, see Section 4.3.1.) 4.3.2. Berkeley Design Tools The Berkeley VLSI tools consist of programs that help IC designers in all steps of the design process, from initial design steps to analysis of complete VLSI circuits. These tools were developed in the EECS department of the University of California at Berkeley. New tools, OCT and VEM (a design database manager) have been released to further integrate their VLSI CAD environment. 4.3.2.1. Magic Magic is the backbone of the Berkeley integrated circuit CAD software system. It evolved from Caesar, an earlier VLSI graphical editor. With Magic, designers can paint geometry using a mouse and a graphic display system. While Caesar was a simple "what-you-paint" is "what-you-get" scheme, Magic is an "abstract log" type graphic editor. The layers painted are not the actual mask layers used in fabrication. The actual GDSII or CIF layers are generated by Magic from the abstract layers. For example a poly-to-metal contact is drawn and shown as one layer, but the Magic GDSII (or CIF) writer generates the three layers used in fabrication (poly, metal, and the contact cut between them). Designs done with other design tools may be read into Magic via the CIF or GDSII formats. Make sure the lambda scaling and technology match those in Magic. To successfully read a layout done with other tools into Magic, you need a thorough understanding of how Magic interprets CIF and GDSII. 4.3.3. SPICE SPICE was originally developed at the University of California at Berkeley. Several versions of SPICE are available from the University. The most current are SPICE2g6 (written in FORTRAN) and SPICE3a7 (written in C). Both versions of SPICE will run on various systems running 4.2/4.3 bsd UNIX, as well as on machines running VMS. Both versions are distributed by the University of California, EECS Department. MOSIS provides SPICE (Level 2) model parameters (obtained from wafer measurements) for each fabrication run. MOSIS has supplemented SPICE with BSIM parameters for CMOS 2.0, 1.6, and 1.2 micron runs to obtain better simulation results for short channel devices. 4.3.4. Other Public Domain Design Tools Many universities have also developed CAD tools to facilitate VLSI designs. Stanford University has software which centers on device simulation and model parameter extraction (e.g., ADLIB/SABLE, PISCES, SUPREM). The University of Washington/Northwest (UW/NW) VLSI Consortium puts out a set of VLSI design tools based on the Berkeley Caesar/Magic tool set. One tool of particular interest is a padframe generator that is compatible with MOSIS' Standard Frames. This consortium also provides other macro generators. The Massachusetts Institute of Technology (MIT) also has a set of design tools (e.g., RSIM). Carnegie-Mellon University (CMU) has a set of CAD tools developed as part of their SRC Research Center for CAD. 4.4. For More Information For more information on commercial CAD vendors that can be used with MOSIS, see Chapter 4 (Section 4.4). For more information about HSPICE, contact: Meta-Software, Inc. 50 Curtner Avenue, Suite 16 Campbell, CA 95008 Tel: (408) 371-5100 For more information on obtaining Berkeley VLSI Tools, including Magic, SPICE, OCT, and VEM, contact: Industrial Liaison Program/Software Distribution 479 Cory Hall Department of EECS University of California Berkeley, CA 94720 Tel: (415) 643-6687 For more information about University of Washington Tools, contact: Northwest Lab for Integrated Systems Department of CS, FR-35 University of Washington Seattle, WA 98195 Tel: (206) 545-3796 For more information about Stanford tools, contact: Office of Technology Licensing Software Distribution Center Stanford University Stanford, CA 94306 Tel: (415) 723-0651 For more information about MIT tools, contact: Massachusetts Institute of Technology VLSI Tools Release Microsystems Research Center Room 39-321 Cambridge, MA 02139 Tel: (617) 253-8138 For more information about CMU's tools, including COSMOS, contact: CMU Research Center for CAD Carnegie-Mellon University Pittsburgh, MA 15213 Tel: (412) 268-3617 Index Berkeley VLSI Design Tools 25 BSIM 25 CIF 24 CMOS3 Cell Library 25 Design rules 24 GDSII 24 HSPICE 25 Magic 25 Public domain design tools 25 SPICE 24, 25 VLSI CAD tools 24 Table of Contents 4. VLSI CAD Tools 24 4.1. Introduction 24 4.2. Commercial VLSI CAD Tools for Use with MOSIS 24 4.2.1. Circuit Simulation 24 4.3. Public Domain VLSI CAD Tools for Use with MOSIS 25 4.3.1. CMOS3 Cell Library 25 4.3.2. Berkeley Design Tools 25 4.3.2.1. Magic 25 4.3.3. SPICE 25 4.3.4. Other Public Domain Design Tools 25 4.4. For More Information 25 Index 27