MOSIS TOPICS Chapter titles are listed where topics correspond to particular chapters in the MOSIS User Manual. Other technical materials which are not found in the User Manual are listed by appropriate category, e.g., Magic technology files are listed in the VLSI CAD Tools Section. PLEASE NOTE: The 'Announcements' file contains copies of important recent notices to MOSIS Users and Liaisons, e.g., updates of Fabrication and Price Schedules, new options. It's a good review of recent changes and trends. CATEGORY TOPIC-NAME TOPIC ------------------------------------------------------------------------- I. INTRODUCTION - WHAT IS MOSIS? GENERAL Brief description of the MOSIS Service. MOSIS_TECH Technology descriptions and project submission specifications. Includes information on wafer acceptance specifications. PRICE_SCHED Price list for all MOSIS technologies. SAMPLE_FORMS Sample MOSIS forms. Be sure to get the MOST UPDATED forms from MOSIS since MOSIS schedules are often revised. SCHEDULE Fabrication schedule/design submittal deadlines. SUBCONTRACTORS List of MOSIS subcontractors. TEMPLATES Various MOSIS REQUEST templates (particularly useful to infrequent users). II. GETTING STARTED GETTING_STARTED Describes how to become an authorized MOSIS User. III. COMMUNICATING WITH MOSIS A. PROJECT SUBMISSION PROJ_SUB For offline and network users. For online users, includes mail size limits, address syntax, discussion of all kinds of networks. B. MOSIS MAIL SYSTEM MOSIS_MAIL Describes the MOSIS online request message system; includes project submission sequence and list of MOSIS requests. C. GDSII and CIF CONVENTIONS GDSII_CIF Conventions for file transmission, also information on CIF-FTP, CIF-CHECKSUM, and the differences between CIF2<.0 and MOSIS' variant, CIF 2.7.1. IV. DESIGNING YOUR CHIP A. CHIP SIZES AND QUANTITIES CHIP_SZES_QUANTS Describes various MOSIS chip sizes and standard quantities. B. DESIGN RULES SCRULES6 MOSIS Scalable CMOS design rules (Rev6). SCRULES_ELECTRODE MOSIS Scalable CMOS Electrode second poly layer design rules; includes capacitor, gate and contact. SCRULES_NPN MOSIS preliminary rules for NPN transistors. SCRULES_CCD MOSIS preliminary rules for buried CCD. SCRULES_HISTORY History of design rule changes; listing of separate design rule pages. VENDOR_SPECS Vendor electrical specifications for all MOSIS 3.0, 2.0, 1.6 and 1.2 micron CMOS double metal vendors. VENDOR_PRM MOSIS measured parameters including electrical characterisics and SPICE (LEVEL 2 and/or BSIM) model decks. BSIM_HSPICE Discusses use of BSIM model parameters with HSPICE; includes a C program which translates BSIM file to the format usable by HSPICE. C. TECHNOLOGY CMOSBK Scalable and Nonscalable CMOS: includes discussion of electrical and SPICE parameters, geometry layers and grids. FOUNDRY A list of foundries (for designers who want to design for a particular foundry). GALLIUM_ARSENIDE Information on MOSIS new GaAs runs. LOW_NOISE_ANALOG Description of MOSIS' Low Noise Analog technology. SCMOS_MANUAL Magic Technology Manual (Scalable CMOS) TINYCHIP Describes MOSIS' smallest chip size and tells you how to submit your projects. D. LIBRARIES LIBRARIES Introduction to MOSIS Libraries, both Supported and Unsupported. LIBDIRECTORY Files currently available through the LIBRARY request (updated daily). E. VLSI CAD TOOLS VLSICAD_TOOLS Very general overview of available CAD tools for use with MOSIS. MAGIC Discussion of Magic Technology files. for SCMOS. V. FABRICATING YOUR CHIP MOSIS_PACKAGING List of types/characteristics of MOSIS-supplied packages; also discussion of user or vendor-supplied packages. 84PIN_LAYOUT Layout of the MOSIS-supplied 84 pin grid array package. 108PIN_LAYOUT Layout of the 108-pin-grid-array package supplied by MOSIS. 132PIN_LAYOUT Layout of the 132-pin-grid-array package supplied by MOSIS. PACK_BOND General information on packaging and bonding; includes Standard and Nonstandard Frames. SPECIAL_REQ Lists various special requests, e.g., no bonding, refabrication of your chip. ALL-RUNS Status of all runs, including those already completely distributed to designers. run.STS Status of the run named "run" (the name of the run (wafer lot) for a particular fabricated device is the first four characters of its "Fab-ID", e.g., "M11X"). STATUS Status of current runs, i.e., those runs not completely distributed to designers. VI. OTHER SERVICES FUNCTIONAL_SCREEN Wafer screening for quantity production. FUSION Short description of this automatic placement and routing service. FUSION_MANUAL Complete FUSION document. NETLIST_TO_PARTS Description of MOSIS' new Netlist-to- Parts service - the integration of the CMOSN Cell Library into major CAE/CAD vendors. VII. TESTING RUN.PRM The electrical parameters for the run named "run" (e.g., M11X). (The name of the run (wafer lot) for a particular fabricated device is the first four characters of its "Fab-ID", e.g., "M11X"). PROCESS_MONITOR Description of MOSIS' process monitor. VIII. OTHER TOPICS ANNOUNCEMENTS Copies of current MOSIS announcements which might include: updates of Price and Fabrication Schedules, notices of new available options and experimental runs. MOSIS_BBOARD Instructions on how to send mail to and receive copies of the MOSIS BBoard. MOSIS_GLOSSARY Contains a list of terms and their descriptions as used by the MOSIS Service. DIRECTORY Information files currently available through the INFORMATION request (updated daily). PCB Information on PCB fab. TOPICS This information. USER_MANUAL General information including MOSIS network interaction. MANUAL_UPDATES Summary of all changes in Release 3.1. To request any of the above information, send an Internet message to MOSIS@MOSIS.EDU including the following lines in the body: REQUEST: INFORMATION TOPIC: Topic-name, Topic-name, Topic-name, etc. REQUEST: END where "Topic-name" is one of the names given above. MOSIS will then mail the topic(s) information to the sender of the request.