1.4 Mentor Graphics & MOSIS (Contributed by Sue Drouin of Mentor Graphics) Mentor Graphics Higher Education Program, recognizing the need to better support universities in the area of IC design, layout and fabrication, kicked off a MOSIS project in the summer of 1992. We have been working closely with several universities to define, study and recommend solutions in three key areas: CIF format, technology files, and documentation. Mentor Graphics currently offers two software applications that address IC design. GDT Designer if you are working in an object oriented environment or IC Station if you are working with polygons (traditional layout). The current release of GDT Designer includes the capability to output in CIF format. The V8.2 release of IC Station will also include CIF format capability. In the area of technology files, university developed files are being shared with other program participants. These files will contain the necessary information to be compliant with the MOSIS 1.2 and 2.0 micron processes. In addition, Mentor Graphics is releasing a CMOSN Design Kit, which is detailed below. Documentation is being written by two universities to document a standard design process for both GDT Designer and IC Station. The process will be a Top-Down, Full Custom Layout from schematic capture to layout to chip submission via MOSIS. This documentation will be available in Q1 1993. For more information about the Mentor Graphics Higher Education Program and MOSIS project contact: Sue Drouin Marketing Representative, Higher Education Program Mentor Graphics Corp. Tel: (503) 685-1183 FAX: (503) 685-1510 email: sue_drouin@mentorg.com Page 6 Page 7 Mentor Graphics Corporation has a new version of the CMOSN Standard Cell Design Kit for designing semicustom projects that can be fabricated via MOSIS. A V8.1 Beta or Pre-production release is available to customers now. A V8.2 production release is planned for the first half of 1993. The kit has a list price of $10,000 for a site license and operates on HP400, HP700 and SUN platforms with 32MB RAM and 840MB Hard Disk.#000# Top-down end to end design is supported. Idea Station permits VHDL design entry and schematic capture with Design Architect, and logic simulation with QuickSim II. AutoLogic can be used for logic synthesis and optimization. QuickCheck performs Electrical Rule Checking. QuickPath is used for critical path analysis, and QuickGrade II allows fault grading. IC Station is used for physical design and verification with ICgraph, ICplan, ICblocks and ICverify.#000# Layout vs schematic checking is also supported. For additional information on the CMOSN Design Kit, contact: Don Laughlin Mentor Graphics Tel: (408) 451-5527 FAX: (408) 451-5680 Email: don_laughlin@mentorg.com 1.8 MIT 6.111 Digital Design Tools (Contributed by Don Troxel of M.I.T.) The digital design tools used in MIT's 6.111 course on digital design have been made available via anonymous ftp from sunpal2.mit.edu. They are located in the subdirectory, pub/digital_tools and are in compressed tar format. The software is copyrighted primarily to prohibit sale, but not to prohibit redistribution or use (commercial or otherwise). A paper, which briefly describes the software is "Digital Design Tools", by D. E. Troxel published in the Proceedings of the 1992 Frontiers in Education, 22nd annual conference, IEEE Catalog No. 92CH3210-2 (pp. 737-742). A mailing list has been setup to announce future additions and availability of newer versions. Additions or deletions from this list can be effected by mailing such a request to troxel@mit.edu. Hard copy of the available documentation is available upon request to troxel@mit.edu. Professor Donald E. Troxel 36-287 MIT 50 Vassar Street Cambridge, Mass. 02139 TEL: (617)-253-2570 1.9 WireC: A Graphical/Procedural System for Schematics (Contributed by Larry McMurchie of Univ. of Washington) WireC is a graphical specification language that combines schematics with procedural constructs for describing complex microelectronic systems. WireC allows the designer to choose the appropriate representation, either graphical or procedural, at a fine-grain level depending on the characteristics of the circuit being designed. Drawing traditional schematic symbols and their interconnections provides fast intuitive interaction with a circuit design while procedural constructs give the power and flexibility to describe circuit structures algorithmically and allow single descriptions to represent whole families of devices. The procedural capability of WireC allows other CAD tools to be incorporated into the design system. For example, we have defined an interface to the SIS logic synthesis system wherein the designer can represent part of the system behaviorally. WireC invokes logic synthesis on these components to produce a structural description that can be incorporated into the rest of the design. Libraries of devices defining a particular netlist output format may be defined by the user. The libraries currently distributed with WireC include a default CMOS gate library whose output is the SIM format. This format can be simulated with COSMOS or IRSIM and compared against a circuit extracted from layout. This library also includes devices that allow a behavioral description to be synthesized and mapped using MIS or SIS and incorporated into a larger circuit. Page 11 Page 12 Another library is the xnf library for designing systems with Xilinx FPGAs. Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC, this library contains devices specific to the 2000 and 3000 series Xilinx LCA's. In addition to drawing the devices explicitly, one can represent parts of a circuit with equations and have these synthesized automatically. Currently in progress is a library of CMOS gates for Cascade Design Automation's ChipCrafter product. WireC provides a mixed schematic/procedural design frontend for ChipCrafter, which uses module generation, timing analysis and place and route software to create a physical layout from the WireC design specification. WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed Tellman. We are interested in any libraries you may develop and will provide a limited degree of support. WireC requires an X-Windows compatible environment and a C++ compiler such as Gnu G++ and AT&T CC. WireC is available via ftp on the Internet. For details send mail to: larry@cs.washington.edu or ebeling@cs.washington.edu. 1.10 MacTester: A Low-Cost Functional Tester (Contributed by Larry McMurchie of Univ. of Washington) The MacTester is an interactive software/hardware environment for functionally testing digital systems. The MacTester hardware itself consists of a NuBus interface (or PC/AT ISA interface) and a special tester board that provides 128 bi-directional stimulus/response pins. These pins are software programmable so that a test setup can be changed quickly from one project to another, allowing the tester to be shared among a number of projects or students. The implementation makes extensive use of Field Programmable Gate Arrays (FPGAs) which reduce the part count as well as the board area. The MacTester software provides a platform which can be used to implement multiple testing and debugging environments. The simplest interface to the tester is a library of routines which set values on inputs, return values on outputs, and transfer data between the MacTester board and the host program. The user writes a C program that sets up a test using these routines. Commonly, the expected result is computed at the same time as the DUT is being tested and the results compared on the fly. The library of tester routines also makes possible an interface to a simulation system, allowing test programs written for simulation to be used directly to test a chip or board, perhaps in parallel with a simulation. Another option is a graphical interface, similar to that provided by logic analyzers. Such an interface exists between the MacTester and the simulation environment of DesignWorks/LogicWorks -- a schematic capture and simulation system written for the Macintosh by Capilano Computing of Westminister, B.C., Canada. In DesignWorks, graphical I/O devices such as keypads, displays and timing diagrams are used to interactively test and debug a circuit. Any device or board plugged into the MacTester can be included in the schematic and simulation environment just like any other device. The DesignWorks graphical I/O devices can then be used to test and debug the DUT. Page 12 Page 13 You may have seen the MacTester demonstrated, or heard one of us talk about it at the Microelectronics Education Conference a few years ago. Recently, Applied Precision, Inc. of Mercer Island, WA has begin to manufacture and sell the MacTester. Additionally, we have begun a loaner program that allows people to evaluate the MacTester for up to a month. If you are interested in obtaining a TR describing the MacTester in detail, or would like to find out more about the loaner program, send mail to larry@cs.washington.edu. If you are interested in purchasing a MacTester, contact Applied Precision, Inc. 8505 SE 68th St. Mercer Island, WA 98040 (206) 236 0704 Summary of MacTester specs: 128 bidirectional I/O's, TTL/CMOS compatible 20x20 ZIF (zero-insertion-force) socket for test chip Preprogrammed chip interface: virtually no wiring needed for nearly all DIPs and PGAs up to 128 active signals Off-line vector memory: 5400+ vectors @ 800 kHz On-line (program-driven) testing capability: unlimited number of vectors @ 50 kHz C language interface for both on-line and off-line testing Simulator interface to Capilano DesignWorks 32-bit parallel interface to host computer Interfaces to both Macintosh II and IBM-PC/AT compatibles