! A version of MUSA simulation codes for the HEC circuit and the state machine.
! The file is written based on my knowledge of the problem.
! Note that I do not shift in payload data values. As long as I know 
! my first 4 bytes of header are the same as the cell_out, I know I have
! connected my DFFs correctly.

!
! set up signals and basic macros
!
mv out out<7:0>
mv in cell<7:0>
watch out out sync valid bypass cell_ready
!
macro clock
se phi 1
ev
se phi 0
ev
$end
!
macro check
se phi 1
ev
se phi 0
ev
se in $1
ev
$end
!
! set up verification macros
!
macro match1
se in H11
check H22
check H33
check H44
check H63
sh out
rp 45 clock 
$end
!
macro match2
se in H82
check HFF
check HDD
check HCC
check H20
sh out
rp 45 clock 
$end
!
macro mismatch1
se in HAA
check H84
check H74
check H00
check H00
rp 45 clock
sh out 
$end
!
macro mismatch2
se in H00
check H99
check HE4
check HAB
check H00
sh out
rp 45 clock
$end
!
! start simulation
!
! initialize system
!
se in H00
se reset 0 
ev
se reset 1
ev
sh out 
!
se in H00
check H01
check H02
check H03
check HCA ! a match => in PRESYNC
sh out 
!
clock  ! 1st header byte out of all DFFs in HEC Circuit
sh out ! cell_out = H00
!
clock  ! 2nd header byte out of all DFFs in HEC Circuit
sh out ! cell_out = H01 etc.
!
rp 43 clock 
se in HAB
check HE4
check H99
check H00
check H00 ! a mismatch
sh out ! back in HUNT; going to check every byte for match
!
check H01
check H02
check H03
check HCA ! a match
sh out ! back in PRESYNC
!
rp 45 clock
rp 5 match2 ! Have 6 consecutive matches => go to SYNC state : sync =1 
se in H11
ev
check H22
check H33
check H44
check H63
clock ! 1st header byte out of the last DFF in HEC circuit
sh out ! bypass should be 1
!
clock  
sh out ! bypass should be 1
!
clock
sh out ! bypass should be 1
!
clock
sh out ! bypass should be 1
!
clock
sh out ! bypass should be 1
!
rp 44 clock 
mismatch1 ! cell_ready should be 1.
rp 6 mismatch2 ! Have 7 consecutive mismatches => back to HUNT, sync=0 
!