! A version of simulation file for HEC Circuit
! compare previous 4 bytes with present byte
! This simulation file is written based on my knowledge of the HEC circuit

mv in in<7:0>
mv out out<7:0>
mv delay delay1<7:0> delay2<7:0> delay3<7:0> delay4<7:0>
mv crc crc<7:0>
!
macro check
  sh in out delay crc
  se phi 1
  ev
  se phi 0
  ev
  se in $1
  ev
$end
!
se in H00
se reset 0
ev
se reset 1
ev
!
se in H00
check H01
check H02
check H03
check HCA
!
sh crc ! f(H03020100) = HCA
sh match<0> ! f(H03020100) cmp HCA ; should match
!
check H30
sh crc ! f(HCA030201) = H30
sh match<0> ! f(HCA030201) cmp H30 ; should match
sh out ! (out = H00)
!
check H06
sh crc ! f(H30CA0302) = H06
sh match<0> ! f(H30CA0302) cmp H06 ; no match
sh out ! (out = H01)
!
check H17
sh crc ! f(H0630CA03) = H17
sh match<0> ! f(H0630CA03) cmp H17 ; no match
sh out ! (out = H02)
!
check HEA
sh crc ! f(H170630CA) = HEA
sh match<0> ! f(H170630CA) cmp HEA ; should match
sh out ! (out = H03)