running bdsyn to create logic table running espresso to minimize table running misII to synthesize logic WARNING: uses as primary input arrival time the value (0.00,0.00) WARNING: uses as primary input drive the value (0.10,0.10) WARNING: uses as primary output load the value 3.00 WARNING: uses as primary output required time the value (0.00,0.00) running padplace to create i/o list padplace: Message: VERSION 5.4 : Aug 3 1992 Placement of pads for "control:logic:contents;" Random placement: PS<1> (TOP,0.63) Random placement: PS<3> (BOTTOM,0.62) Random placement: PS<2> (BOTTOM,0.26) Random placement: PS<0> (RIGHT,0.43) Random placement: pbytes<1> (BOTTOM,0.76) Random placement: pbytes<0> (BOTTOM,0.37) Random placement: pbytes<5> (TOP,0.76) Random placement: pbytes<4> (BOTTOM,0.19) Random placement: pbytes<3> (BOTTOM,0.54) Random placement: pbytes<2> (LEFT,0.57) Random placement: match (LEFT,0.29) Random placement: sync (RIGHT,0.10) Random placement: valid (BOTTOM,0.76) Random placement: bypass (TOP,0.35) Random placement: cell_ready (RIGHT,0.54) Random placement: NS<3> (LEFT,0.30) Random placement: NS<2> (TOP,0.76) Random placement: NS<1> (RIGHT,0.42) Random placement: NS<0> (TOP,0.48) Random placement: nbytes<5> (LEFT,0.95) Random placement: nbytes<4> (RIGHT,0.02) Random placement: nbytes<3> (BOTTOM,0.70) Random placement: nbytes<2> (BOTTOM,0.08) Random placement: nbytes<1> (BOTTOM,0.14) Random placement: nbytes<0> (LEFT,0.55) running bdnet to wire latches running octflatten octflatten: VERSION 5.00 : Aug 3 1992 running wolfe to place and route cells wolfe version 1.95 last edited 8/14/91 Randomly assigning formal terminal match to BOTTOM at 0.629 Randomly assigning formal terminal reset to RIGHT at 0.624 Randomly assigning formal terminal sync to RIGHT at 0.263 Randomly assigning formal terminal valid to LEFT at 0.430 Randomly assigning formal terminal bypass to RIGHT at 0.756 Randomly assigning formal terminal cell_ready to RIGHT at 0.368 Randomly assigning formal terminal phi to BOTTOM at 0.758 TimberWolfSC version:v4.2c date:Aug 3 1992 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Kai-Win Lee, Bill Swartz, Mindy Lee, and Dahe Chen Yale University 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 formal terminal "Vdd": estimated PEAKCURRENT=0.0294 Amps. formal terminal "GND": estimated PEAKCURRENT=0.0294 Amps. running chipstats