===============================
		Creating a Standard Cell Design
		with the OCTTOOLS
		===============================

		List of Commands
		----------------

1) create the logic table
	vi add.logic

2) reduce the logic table
	espresso add.logic > add.pla

3) reduce logic and create CMOS structure in the logic facet
	misII -f script.msu -t pla -T oct -o add:logic add.pla

4) create a padlist for the cell and put it back in the logic facet
	padplace -l add:logic > add.padlist
	padplace -D add.padlist add:logic

5) flattens the core/processor so routing can be done
	octflatten -t LEAF -o add:flat add:logic

6) routes the core - the facet :placed can now be viewed
	wolfe -f -o add:placed add:flat

7) determine the routing for the chip pad frame
   modify the mosis.net file for correct routing
	vi mosis.net

8) create a frame with the core inside
    VEM must be used to physically route the wires
	bdnet mosis.net

11) once the wires have been routed and fabprep is run,
    the chips is ready for fabrication at MOSIS
	fabprep mosis:symbolic