===============================
		Creating a Standard Cell Design
		with the OCTTOOLS
		===============================

		List of Commands
		----------------

1) create the logic table
	vi logic.orig

2) reduce the logic table
	espresso logic.orig > mult.pla

3) reduce logic and create CMOS structure in the logic facet
	misII -f script.msu -t pla -T oct -o mult:logic mult.pla

4) create a padlist for the cell and put it back in the logic facet
	padplace -l mult:logic > mult.padlist
	padplace -D mult.padlist mult:logic

5) merge the logic instance and flip-flops together
  this goes into a logic facet that can not be viewed
	bdnet mult_cell.net

6) merge the cell instances together
	bdnet mult_proc.net

7) flattens the core/processor so routing can be done
	octflatten -t LEAF -o mult_proc:flat mult_proc:logic

8) routes the core - the facet :placed can now be viewed
	wolfe -f -o mult_proc:placed mult_proc:flat

9) determine the routing for the chip pad frame
   modify the mosis.net file for correct routing
	vi mosis.net

10) create a frame with the core inside
    VEM must be used to physically route the wires
	bdnet mosis.net

11) once the wires have been routed and fabprep is run,
    the chips is ready for fabrication at MOSIS
	fabprep mosis:symbolic