MOSIS PACKAGING
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MOSIS-Supplied Packages

MOSIS offers the following standard commercial packages: 28 or 40 pin DIPs
(Dual In-line Package) and 65, 84, 108, or 132 PGAs (Pin Grid Array). The
package selected for a specific project depends on the number of pads in your
design and on the size of the chip. MOSIS uses ceramic, cavity-up packages; the
DIP packages are side-brazed. The following summarizes package characteristics.

PIN	CAVITY		LEAD		LEAD		THERMAL
COUNT	SIZE		RESISTANCE	INDUCTANCE	RESISTANCE
-----	------		----------	----------	----------
28 DIP  .310 x .310"	350 mOHM	- -		55 deg C/W

40 DIP	.310 x .310"	500 mOHM	- -		45 deg C/W

65 PGA	.400 x .400"	600 mOHM	- -		40 deg C/W

84 PGA	.350 x .350" 	600 mOHM	7 nH		40 deg C/W

84 PGA	.470 x .470"	600 mOHM	7 nH		40 deg C/W

108 PGA	.350 x .350"	600 mOHM	11 nH		35 deg C/W

108 PGA	.450 x .450"	600 mOHM	11 nH		35 deg C/W

132 PGA	.350 x .350" 	1500 mOHM	19 nH		35 deg C/W

132 PGA	.450 x .450"	1500 mOHM	19 nH		35 deg C/W

Note: Lead resistances and inductances are for signal lines, values for
selected pins are lower. The junction to ambient (theta ja) thermal resistance
is based upon a 10,000 square mil die, board mounted in still air. Thermal
resistance varies with materials used, die size, process technology, air
circulation and heat dissipation characteristics of the device.