#
# Formal Terminal description for stage3:logic
# padp recognizes the following keywords:
# TERMTYPE (SUPPLY | GROUND | SIGNAL | CLOCK) : DEFAULT = SIGNAL
# DIRECTION (INPUT | OUTPUT | INOUT) : DEFAULT = INOUT
# PEAKCURRENT ( x (in Amperes)) : DEFAULT = 0.0
#   NOTE: PEAKCURRENT applies only to SUPPLY and GROUND terminals
# TERM_FLOATING_EDGES (ALL | {LEFT|RIGHT|TOP|BOTTOM})
# TERM_EDGE (LEFT | RIGHT | TOP | BOTTOM) : DEFAULT = none
# TERM_ROW ( 0 | 1 | 2 | ... | n) : DEFAULT = 0
# TERM_RELATIVE_POSITION ( 0.0 <= x <= 1.0) : DEFAULT = none
# TERM_RELATIVE_POSITION_STEP ( 0.0 <= x <= 1.0) : DEFAULT = 0.0

# This file uses a 'REVERSE' logic: 
# First you specify the properties
# then the terminal for which the props apply
	TERMTYPE SIGNAL
	DIRECTION INPUT
FORMAL_TERMINAL b1<7>
FORMAL_TERMINAL b1<6>
FORMAL_TERMINAL b1<5>
FORMAL_TERMINAL b1<4>
FORMAL_TERMINAL b1<3>
FORMAL_TERMINAL b1<2>
FORMAL_TERMINAL b1<1>
FORMAL_TERMINAL b1<0>
FORMAL_TERMINAL b2<7>
FORMAL_TERMINAL b2<6>
FORMAL_TERMINAL b2<5>
FORMAL_TERMINAL b2<4>
FORMAL_TERMINAL b2<3>
FORMAL_TERMINAL b2<2>
FORMAL_TERMINAL b2<1>
FORMAL_TERMINAL b2<0>
FORMAL_TERMINAL b3<7>
FORMAL_TERMINAL b3<6>
FORMAL_TERMINAL b3<5>
FORMAL_TERMINAL b3<4>
FORMAL_TERMINAL b3<3>
FORMAL_TERMINAL b3<2>
FORMAL_TERMINAL b3<1>
FORMAL_TERMINAL b3<0>
FORMAL_TERMINAL b4<7>
FORMAL_TERMINAL b4<6>
FORMAL_TERMINAL b4<5>
FORMAL_TERMINAL b4<4>
FORMAL_TERMINAL b4<3>
FORMAL_TERMINAL b4<2>
FORMAL_TERMINAL b4<1>
FORMAL_TERMINAL b4<0>
FORMAL_TERMINAL b5<7>
FORMAL_TERMINAL b5<6>
FORMAL_TERMINAL b5<5>
FORMAL_TERMINAL b5<4>
FORMAL_TERMINAL b5<3>
FORMAL_TERMINAL b5<2>
FORMAL_TERMINAL b5<1>
FORMAL_TERMINAL b5<0>
FORMAL_TERMINAL b6<7>
FORMAL_TERMINAL b6<6>
FORMAL_TERMINAL b6<5>
FORMAL_TERMINAL b6<4>
FORMAL_TERMINAL b6<3>
FORMAL_TERMINAL b6<2>
FORMAL_TERMINAL b6<1>
FORMAL_TERMINAL b6<0>
FORMAL_TERMINAL b7<7>
FORMAL_TERMINAL b7<6>
FORMAL_TERMINAL b7<5>
FORMAL_TERMINAL b7<4>
FORMAL_TERMINAL b7<3>
FORMAL_TERMINAL b7<2>
FORMAL_TERMINAL b7<1>
FORMAL_TERMINAL b7<0>
FORMAL_TERMINAL b8<7>
FORMAL_TERMINAL b8<6>
FORMAL_TERMINAL b8<5>
FORMAL_TERMINAL b8<4>
FORMAL_TERMINAL b8<3>
FORMAL_TERMINAL b8<2>
FORMAL_TERMINAL b8<1>
FORMAL_TERMINAL b8<0>
FORMAL_TERMINAL b9<7>
FORMAL_TERMINAL b9<6>
FORMAL_TERMINAL b9<5>
FORMAL_TERMINAL b9<4>
FORMAL_TERMINAL b9<3>
FORMAL_TERMINAL b9<2>
FORMAL_TERMINAL b9<1>
FORMAL_TERMINAL b9<0>
FORMAL_TERMINAL b10<7>
FORMAL_TERMINAL b10<6>
FORMAL_TERMINAL b10<5>
FORMAL_TERMINAL b10<4>
FORMAL_TERMINAL b10<3>
FORMAL_TERMINAL b10<2>
FORMAL_TERMINAL b10<1>
FORMAL_TERMINAL b10<0>
FORMAL_TERMINAL b11<7>
FORMAL_TERMINAL b11<6>
FORMAL_TERMINAL b11<5>
FORMAL_TERMINAL b11<4>
FORMAL_TERMINAL b11<3>
FORMAL_TERMINAL b11<2>
FORMAL_TERMINAL b11<1>
FORMAL_TERMINAL b11<0>
FORMAL_TERMINAL b12<7>
FORMAL_TERMINAL b12<6>
FORMAL_TERMINAL b12<5>
FORMAL_TERMINAL b12<4>
FORMAL_TERMINAL b12<3>
FORMAL_TERMINAL b12<2>
FORMAL_TERMINAL b12<1>
FORMAL_TERMINAL b12<0>
FORMAL_TERMINAL b13<7>
FORMAL_TERMINAL b13<6>
FORMAL_TERMINAL b13<5>
FORMAL_TERMINAL b13<4>
FORMAL_TERMINAL b13<3>
FORMAL_TERMINAL b13<2>
FORMAL_TERMINAL b13<1>
FORMAL_TERMINAL b13<0>
FORMAL_TERMINAL b14<7>
FORMAL_TERMINAL b14<6>
FORMAL_TERMINAL b14<5>
FORMAL_TERMINAL b14<4>
FORMAL_TERMINAL b14<3>
FORMAL_TERMINAL b14<2>
FORMAL_TERMINAL b14<1>
FORMAL_TERMINAL b14<0>
FORMAL_TERMINAL reset
	DIRECTION OUTPUT
FORMAL_TERMINAL output3<7>
FORMAL_TERMINAL output3<6>
FORMAL_TERMINAL output3<5>
FORMAL_TERMINAL output3<4>
FORMAL_TERMINAL output3<3>
FORMAL_TERMINAL output3<2>
FORMAL_TERMINAL output3<1>
FORMAL_TERMINAL output3<0>
FORMAL_TERMINAL c1<7>
FORMAL_TERMINAL c1<6>
FORMAL_TERMINAL c1<5>
FORMAL_TERMINAL c1<4>
FORMAL_TERMINAL c1<3>
FORMAL_TERMINAL c1<2>
FORMAL_TERMINAL c1<1>
FORMAL_TERMINAL c1<0>
FORMAL_TERMINAL c2<7>
FORMAL_TERMINAL c2<6>
FORMAL_TERMINAL c2<5>
FORMAL_TERMINAL c2<4>
FORMAL_TERMINAL c2<3>
FORMAL_TERMINAL c2<2>
FORMAL_TERMINAL c2<1>
FORMAL_TERMINAL c2<0>
FORMAL_TERMINAL c3<7>
FORMAL_TERMINAL c3<6>
FORMAL_TERMINAL c3<5>
FORMAL_TERMINAL c3<4>
FORMAL_TERMINAL c3<3>
FORMAL_TERMINAL c3<2>
FORMAL_TERMINAL c3<1>
FORMAL_TERMINAL c3<0>
FORMAL_TERMINAL c4<7>
FORMAL_TERMINAL c4<6>
FORMAL_TERMINAL c4<5>
FORMAL_TERMINAL c4<4>
FORMAL_TERMINAL c4<3>
FORMAL_TERMINAL c4<2>
FORMAL_TERMINAL c4<1>
FORMAL_TERMINAL c4<0>
FORMAL_TERMINAL c5<7>
FORMAL_TERMINAL c5<6>
FORMAL_TERMINAL c5<5>
FORMAL_TERMINAL c5<4>
FORMAL_TERMINAL c5<3>
FORMAL_TERMINAL c5<2>
FORMAL_TERMINAL c5<1>
FORMAL_TERMINAL c5<0>
FORMAL_TERMINAL c6<7>
FORMAL_TERMINAL c6<6>
FORMAL_TERMINAL c6<5>
FORMAL_TERMINAL c6<4>
FORMAL_TERMINAL c6<3>
FORMAL_TERMINAL c6<2>
FORMAL_TERMINAL c6<1>
FORMAL_TERMINAL c6<0>
FORMAL_TERMINAL c7<7>
FORMAL_TERMINAL c7<6>
FORMAL_TERMINAL c7<5>
FORMAL_TERMINAL c7<4>
FORMAL_TERMINAL c7<3>
FORMAL_TERMINAL c7<2>
FORMAL_TERMINAL c7<1>
FORMAL_TERMINAL c7<0>
FORMAL_TERMINAL c8<7>
FORMAL_TERMINAL c8<6>
FORMAL_TERMINAL c8<5>
FORMAL_TERMINAL c8<4>
FORMAL_TERMINAL c8<3>
FORMAL_TERMINAL c8<2>
FORMAL_TERMINAL c8<1>
FORMAL_TERMINAL c8<0>
FORMAL_TERMINAL c9<7>
FORMAL_TERMINAL c9<6>
FORMAL_TERMINAL c9<5>
FORMAL_TERMINAL c9<4>
FORMAL_TERMINAL c9<3>
FORMAL_TERMINAL c9<2>
FORMAL_TERMINAL c9<1>
FORMAL_TERMINAL c9<0>
FORMAL_TERMINAL c10<7>
FORMAL_TERMINAL c10<6>
FORMAL_TERMINAL c10<5>
FORMAL_TERMINAL c10<4>
FORMAL_TERMINAL c10<3>
FORMAL_TERMINAL c10<2>
FORMAL_TERMINAL c10<1>
FORMAL_TERMINAL c10<0>
FORMAL_TERMINAL c11<7>
FORMAL_TERMINAL c11<6>
FORMAL_TERMINAL c11<5>
FORMAL_TERMINAL c11<4>
FORMAL_TERMINAL c11<3>
FORMAL_TERMINAL c11<2>
FORMAL_TERMINAL c11<1>
FORMAL_TERMINAL c11<0>
FORMAL_TERMINAL c12<7>
FORMAL_TERMINAL c12<6>
FORMAL_TERMINAL c12<5>
FORMAL_TERMINAL c12<4>
FORMAL_TERMINAL c12<3>
FORMAL_TERMINAL c12<2>
FORMAL_TERMINAL c12<1>
FORMAL_TERMINAL c12<0>
FORMAL_TERMINAL c13<7>
FORMAL_TERMINAL c13<6>
FORMAL_TERMINAL c13<5>
FORMAL_TERMINAL c13<4>
FORMAL_TERMINAL c13<3>
FORMAL_TERMINAL c13<2>
FORMAL_TERMINAL c13<1>
FORMAL_TERMINAL c13<0>
	TERMTYPE SUPPLY
	DIRECTION INPUT
FORMAL_TERMINAL Vdd
	TERMTYPE GROUND
FORMAL_TERMINAL GND
	TERMTYPE CLOCK
FORMAL_TERMINAL clk1
FORMAL_TERMINAL clk2