Network Integrated Processing
Investigators:
Joseph B. Evans, Douglas Niehaus, Victor S. Frost, David W. Petr

This research will develop methods of fully integrating general purpose
processing and memory elements with gigabit local and wide area networks.
A distinguishing aspect of this work is the innovative use of the virtual
circuit capabilities of B-ISDN services provided by asynchronous transfer
mode (ATM) networks to provide connectivity, in combination with new
approaches to protocols, buffering, and caching. We call this approach
Network Integrated Processing (NIP), since it eliminates the dichotomy
between the processor and the network.
The NIP architectural approach creates a distributed computation
environment within which:
Creating the NIP architecture will advance the state of the art in
several areas, including:
The proposed research will be driven and validated by its application to
selected problems from the MAGIC gigabit testbed and DREN testbed
community. We envision the project having three phases: design and
analysis, prototype implementation, and performance measurement and
analysis.
Related Information

Send comments to Joseph B. Evans,
<evans@eecs.ku.edu> .