Program Schedule

Thursday, 12^th June, 2014
9:05am - 9:20am	Opening remarks
9:20am - 10:20am	Keynote: Dr. David Whalley
10:20am - 10:50am	Break
10:50am - 12:05pm	Code Generation and Optimization
12:05pm - 1:35pm	Lunch
1:35pm - 2:50pm	Worst Case Timing Analysis
2:50pm - 3:20pm	Break
3:20pm - 4:10pm	Search Space Exploration
Friday, 13^th June, 2014
9:20am - 10:20am	Keynote: Dr. Minyi Guo
10:20am - 10:50am	Break
10:50am - 12:05pm	Static Analysis and Optimization
12:05pm - 1:35pm	Lunch
1:35pm - 2:50pm	Many-core, GPU, and VLIW
2:50pm - 3:20pm	Break
3:20pm - 4:10pm	Memory Optimization and Management

Thursday, 12^th June, 2014

Keynote: Dr. David Whalley -- Energy Efficient Data Access Techniques (Time: 9:20am - 10:20am)

Code generation and optimization (Time: 10:50am - 12:05pm)

1. Efficient Code Generation in a Region-Based Dynamic Binary Translator.

Tom Spink (University of Edinburgh); Harry Wagstaff (University of Edinburgh); Bjorn Franke (University of Edinburgh); Nigel Topham (University of Edinburgh)

2. CASM - Optimized Compilation of Abstract State Machines.

Roland Lezuo (Institute of Computer Languages, Vienna University of Technology); Philipp Paulweber (Institute of Computer Languages, Vienna University of Technology); Andreas Krall (TU Wien)

3. Combinatorial Spill Code Optimization and Ultimate Coalescing.

Roberto Castaneda Lozano (SICS); Mats Carlsson (SICS); Gabriel Hjort Blindell (KTH Royal Institute of Technology); Christian Schulte (KTH Royal Institute of Technology)

Worst case timing analysis (Time: 1:35pm - 2:50pm)

4. Cache Related Preemption Delay analysis for FIFO caches.

Clement Ballabriga (National University of Singapore); Lee Kee Chong (National University of Singapore); Abhik Roychoudhury (National University of Singapore)

5. How to compute worst-case execution time by optimization modulo theory and a clever encoding of program semantics.

Julien Henry (University de Grenoble / Verimag); Mihail Asavoae (Verimag); David Monniaux (CNRS / VERIMAG); Claire Maiza (INP Grenoble / Verimag)

6. WCET-Aware Dynamic Instruction Cache Locking.

Wenguang Zheng (The University of New South Wales); Hui Wu (The University of New South Wales)

Search Space exploration (Time: 3:20pm - 4:10pm)

7. Exploration of Compiler Optimization Sequences using Clustering-Based Selection.

Luiz Martins (Universidade Federal de Uberlandia); Ricardo Nobre (INESC-ID); Alexandre Delbem (ICMC, USP); Eduardo Marques (University of Sao Paulo); Joao Cardoso (FEUP/Universidade do Porto)

8. Partitioning data-parallel programs for heterogeneous MPSOCs : Time and energy design space exploration.

Kiran Chandramohan (University of Edinburgh); Michael O'Boyle (University of Edinburgh)

Friday, 13^th June, 2014

Keynote: Dr. Minyi Guo -- Energy Efficient Data Access and Storage through HW/SW Co-design (Time: 9:20am - 10:20am)

Static analysis and optimization (Time: 10:50am - 12:05pm)

9. Exploiting Function Similarity for Code Size Reduction.

Tobias Edler von Koch (University of Edinburgh); Bjorn Franke (University of Edinburgh); Pranav Bhandarkar (Qualcomm Innovation Centre, Inc); Anshuman Dasgupta (Qualcomm Innovation Centre, Inc)

10. ASAC: Automatic Sensitivity Analysis for Approximate Computing.

Pooja Roy (National University of Singapore); Rajarshi Ray (National Institute of Technology, Meghalaya); Chundong Wang (National University of Singapore); Weng-Fai Wong (National University of Singapore)

11. em-SPADE: A Compiler Extension for Checking Rules Extracted from Processor Specifications.

Sandeep Chaudhary (University of Waterloo); Sebastian Fischmeister (University of Waterloo); Lin Tan (University of Waterloo)

Many-core, GPU, and VLIW (Time: 1:35pm - 2:50pm)

12. VOBLA: A Vehicle for Optimized Basic Linear Algebra.

Ulysse Beaugnon (ENS); Alexey Kravets (ARM LTD); Sven van Haastregt (ARM LTD); Riyadh Baghdadi (ENS); David Tweed (ARM LTD); Javed Absar (ARM LTD); Anton Lokhmotov (ARM LTD)

13. A Framework to Schedule Parametric Dataflow Applications on Many-Core Platforms.

Vagelis Bebelis (INRIA); Pascal Fradet (INRIA); Alain Girault (INRIA)

14. Improving Performance of Loops on DIAM-based VLIW Architecture.

Jinyong Lee (Seoul National University); Jongwon Lee (Seoul National University); Jongeun Lee (Ulsan National Institute of Science and Technology); Yunheung Paek (Seoul National University)

Memory optimization and management (Time: 3:20pm - 4:10pm)

15. Superoptimization of Memory Subsystems.

Joseph Wingbermuehle (Washington University); Ron Cytron (Washington University); Roger Chamberlain (Washington University)

16. Lightweight and Block-level Concurrent Sweeping for JavaScript Garbage Collection.

Hongjune Kim (Seoul National University); Seonmyeong Bak (Seoul National University); Jaejin Lee (Seoul National University)