ITTC Project


Investigation of FPGA Rapid Prototyping of Military Software Radio Systems

Project Award Date: 04-20-1998



Description

The objective of this effort is to develop efficient signal processing algorithms for military tactical radio systems. Specifically, we will implement a rapid prototyping system using both state-of-the-art Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs) and demonstrate the capability of this system to prototype a limited digital radio transmitter and receiver system.

Previous research efforts with Rome Laboratories have led to the development of a digital signal processing rapid prototyping system consisting of Cadence Systems Signal Processing Worksystems (SPW), and Synopsys software tools, with algorithms implemented on FPGAs and paralled-DSP processors. With this system we developed and tested radio algorithms for several of the Air Force's "Smart Radio" programs. With the use of FPGAs, we are investigating ways to speed up the radio algorithms and to reduce the signal processing tasks required of the DSP processor.

The scope of the present effort includes the development, implementation, and demonstration of an operating prototype of a limited-capability digital radio transmitter/receiver system. This demonstration prototype is to be developed using the DSP and FPGA Evaluation and Prototyping System to achieve an optimal system configuration. The effort will look at which radio functions should be partitioned to the DSPs and which functions to the FPGAs.

Another component of the research focuses on interference excission. An essential requirement in military communications is extraction of interference from the received signal as early in the detection process as possible. Military radio systems employ spread spectrum techniques, which produce extremely wide bandwidth signals. To excise interference at spread spectrum bandwidths, high speed digital signal processing is required. The processing speeds needed for interference excision at the spread bandwidth normally exceed those available in traditional DSP microporcessors. Therefore, we are investigating the implementation of certain interference excision algorithms using FPGA technology to facilitate the rapid (and possibly adaptive) excision of narrow band interferers within a large operating bandwidth.


Investigators

Faculty Investigator(s): Glenn Prescott (PI)


Project Sponsors


Primary Sponsor(s): USAF Rome Lab


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